--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
-@@ -98,6 +98,7 @@
+@@ -98,6 +98,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
struct regulator *vdda;
struct regulator *vdda_phy;
struct regulator *vdda_refclk;
-@@ -275,6 +276,10 @@
+@@ -275,6 +276,10 @@ static int qcom_pcie_get_resources_2_1_0
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
-
+
+ res->ext_reset = devm_reset_control_get(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
-@@ -288,6 +293,7 @@
+@@ -288,6 +293,7 @@ static void qcom_pcie_deinit_2_1_0(struc
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
reset_control_assert(res->pci_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
-@@ -306,6 +312,12 @@
+@@ -306,6 +312,12 @@ static int qcom_pcie_init_2_1_0(struct q
u32 val;
int ret;
-
+
+ ret = reset_control_assert(res->ahb_reset);
+ if (ret) {
+ dev_err(dev, "cannot assert ahb reset\n");
ret = regulator_enable(res->vdda);
if (ret) {
dev_err(dev, "cannot enable vdda regulator\n");
-@@ -324,16 +336,16 @@
+@@ -324,16 +336,16 @@ static int qcom_pcie_init_2_1_0(struct q
goto err_vdda_phy;
}
-
+
- ret = reset_control_assert(res->ahb_reset);
+ ret = reset_control_deassert(res->ext_reset);
if (ret) {
+ dev_err(dev, "cannot assert ext reset\n");
+ goto err_reset_ext;
}
-
+
ret = clk_prepare_enable(res->iface_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable iface clock\n");
- goto err_assert_ahb;
+ goto err_iface;
}
-
+
ret = clk_prepare_enable(res->core_clk);
-@@ -422,7 +434,9 @@
+@@ -422,7 +434,9 @@ err_clk_phy:
clk_disable_unprepare(res->core_clk);
err_clk_core:
clk_disable_unprepare(res->iface_clk);