- clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->aux_clk);
- clk_disable_unprepare(res->ref_clk);
- regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
- }
-@@ -321,47 +310,45 @@ static int qcom_pcie_init_2_1_0(struct q
+ writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+@@ -334,47 +323,45 @@ static int qcom_pcie_init_2_1_0(struct q
return ret;
}
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-@@ -393,36 +380,6 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -406,36 +393,6 @@ static int qcom_pcie_init_2_1_0(struct q
val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
usleep_range(1000, 1500);
-@@ -435,15 +392,19 @@ static int qcom_pcie_init_2_1_0(struct q
+@@ -448,15 +405,19 @@ static int qcom_pcie_init_2_1_0(struct q
return 0;