layerscape: update patches-4.14 to LSDK 19.03

[openwrt/staging/jogo.git] / target / linux / layerscape / patches-4.14 / 811-clock-support-layerscape.patch

diff --git a/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch b/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
index dcd1535601966aa6dcc6c7786bbfdc7fb163cb98..331c77c80a26d305f29b2c045524d077826cd225 100644 (file)
--- a/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
@@ -1,14 +1,18 @@
-From d94f8863307c0f7fb7aeb2084cc666c47991d78b Mon Sep 17 00:00:00 2001
+From a00c035c7b82f51716a1a30637b1bd276dee3c5a Mon Sep 17 00:00:00 2001
 From: Biwen Li <biwen.li@nxp.com>
-Date: Mon, 19 Nov 2018 10:26:57 +0800
+Date: Wed, 17 Apr 2019 18:58:17 +0800
 Subject: [PATCH] clock: support layerscape
+
 This is an integrated patch of clock for layerscape
 
-Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
 Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
+Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
+Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
 ---
- drivers/clk/clk-qoriq.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
+ drivers/clk/clk-qoriq.c         | 25 ++++++++++++++++++++++---
+ drivers/cpufreq/qoriq-cpufreq.c |  1 +
+ 2 files changed, 23 insertions(+), 3 deletions(-)
 
 --- a/drivers/clk/clk-qoriq.c
 +++ b/drivers/clk/clk-qoriq.c
@@ -21,7 +25,43 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  };
  
  #define CLKSEL_VALID  1
-@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct
+@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
+       const struct clockgen_muxinfo *cmux_groups[2];
+       const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
+       void (*init_periph)(struct clockgen *cg);
+-      int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
++      int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
+       u32 pll_mask;   /* 1 << n bit set if PLL n is valid */
+       u32 flags;      /* CG_xxx */
+ };
+@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo ch
+               .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+       },
+       {
++              .compat = "fsl,lx2160a-clockgen",
++              .cmux_groups = {
++                      &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
++              },
++              .cmux_to_group = {
++                      0, 0, 0, 0, 1, 1, 1, 1, -1
++              },
++              .pll_mask = 0x37,
++              .flags = CG_VER3 | CG_LITTLE_ENDIAN,
++      },
++      {
+               .compat = "fsl,p2041-clockgen",
+               .guts_compat = "fsl,qoriq-device-config-1.0",
+               .init_periph = p2041_init_periph,
+@@ -601,7 +612,7 @@ static const struct clockgen_chipinfo ch
+                       &p4080_cmux_grp1, &p4080_cmux_grp2
+               },
+               .cmux_to_group = {
+-                      0, 0, 0, 0, 1, 1, 1, 1
++                      0, 0, 0, 0, 1, 1, 1, 1, -1
+               },
+               .pll_mask = 0x1f,
+       },
+@@ -1127,6 +1138,13 @@ static void __init create_one_pll(struct
                struct clk *clk;
                int ret;
  
@@ -35,3 +75,21 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
                snprintf(pll->div[i].name, sizeof(pll->div[i].name),
                         "cg-pll%d-div%d", idx, i + 1);
  
+@@ -1417,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "
+ CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
+ 
+ /* Legacy nodes */
+ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
+--- a/drivers/cpufreq/qoriq-cpufreq.c
++++ b/drivers/cpufreq/qoriq-cpufreq.c
+@@ -320,6 +320,7 @@ static const struct of_device_id node_ma
+       { .compatible = "fsl,ls1046a-clockgen", },
+       { .compatible = "fsl,ls1088a-clockgen", },
+       { .compatible = "fsl,ls2080a-clockgen", },
++      { .compatible = "fsl,lx2160a-clockgen", },
+       { .compatible = "fsl,p4080-clockgen", },
+       { .compatible = "fsl,qoriq-clockgen-1.0", },
+       { .compatible = "fsl,qoriq-clockgen-2.0", },