#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
-@@ -881,7 +881,7 @@ static inline u64 flexcan_read_reg_iflag
+@@ -887,7 +887,7 @@ static inline u64 flexcan_read_reg_iflag
u32 iflag1, iflag2;
iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default &
iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default;
return (u64)iflag2 << 32 | iflag1;
-@@ -931,7 +931,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -937,7 +937,7 @@ static irqreturn_t flexcan_irq(int irq,
reg_iflag2 = priv->read(®s->iflag2);
/* transmission complete interrupt */
u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
handled = IRQ_HANDLED;
-@@ -943,7 +943,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -949,7 +949,7 @@ static irqreturn_t flexcan_irq(int irq,
/* after sending a RTR frame MB is in RX mode */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&priv->tx_mb->can_ctrl);
netif_wake_queue(dev);
}
-@@ -1323,7 +1323,7 @@ static int flexcan_open(struct net_devic
+@@ -1329,7 +1329,7 @@ static int flexcan_open(struct net_devic
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
priv->reg_imask1_default = 0;