u32 reg_ctrl_default;
struct clk *clk_ipg;
-@@ -892,7 +892,8 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -898,7 +898,8 @@ static irqreturn_t flexcan_irq(int irq,
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
irqreturn_t handled = IRQ_NONE;
enum can_state last_state = priv->can.state;
/* reception interrupt */
-@@ -926,10 +927,10 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -932,10 +933,10 @@ static irqreturn_t flexcan_irq(int irq,
}
}
u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
handled = IRQ_HANDLED;
-@@ -941,7 +942,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -947,7 +948,7 @@ static irqreturn_t flexcan_irq(int irq,
/* after sending a RTR frame MB is in RX mode */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&priv->tx_mb->can_ctrl);
netif_wake_queue(dev);
}
-@@ -1226,7 +1227,7 @@ static int flexcan_chip_start(struct net
+@@ -1232,7 +1233,7 @@ static int flexcan_chip_start(struct net
/* enable interrupts atomically */
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
priv->write(upper_32_bits(reg_imask), ®s->imask2);
priv->write(lower_32_bits(reg_imask), ®s->imask1);
enable_irq(dev->irq);
-@@ -1321,6 +1322,7 @@ static int flexcan_open(struct net_devic
+@@ -1327,6 +1328,7 @@ static int flexcan_open(struct net_devic
flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);