#define SDC_FIFO_CFG 0x228
/*--------------------------------------------------------------------------*/
-@@ -249,6 +250,8 @@
+@@ -251,6 +252,8 @@
#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
-@@ -318,6 +321,7 @@ struct msdc_save_para {
+@@ -320,6 +323,7 @@ struct msdc_save_para {
u32 pad_ds_tune;
u32 pad_cmd_tune;
u32 emmc50_cfg0;
u32 sdc_fifo_cfg;
};
-@@ -1747,6 +1751,9 @@ static int msdc_prepare_hs400_tuning(str
+@@ -1750,6 +1754,9 @@ static int msdc_prepare_hs400_tuning(str
writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
/* hs400 mode must set it to 0 */
sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
return 0;
}
-@@ -1997,6 +2004,7 @@ static void msdc_save_reg(struct msdc_ho
+@@ -2000,6 +2007,7 @@ static void msdc_save_reg(struct msdc_ho
host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
}
-@@ -2014,6 +2022,7 @@ static void msdc_restore_reg(struct msdc
+@@ -2017,6 +2025,7 @@ static void msdc_restore_reg(struct msdc
writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);