}
static void mtk_pcie_port_free(struct mtk_pcie_port *port)
-@@ -394,75 +395,6 @@ static struct pci_ops mtk_pcie_ops_v2 =
- .write = mtk_pcie_config_write,
- };
-
--static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
--{
-- struct mtk_pcie *pcie = port->pcie;
-- struct resource *mem = &pcie->mem;
-- const struct mtk_pcie_soc *soc = port->pcie->soc;
-- u32 val;
-- size_t size;
-- int err;
--
-- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
-- if (pcie->base) {
-- val = readl(pcie->base + PCIE_SYS_CFG_V2);
-- val |= PCIE_CSR_LTSSM_EN(port->slot) |
-- PCIE_CSR_ASPM_L1_EN(port->slot);
-- writel(val, pcie->base + PCIE_SYS_CFG_V2);
-- }
--
-- /* Assert all reset signals */
-- writel(0, port->base + PCIE_RST_CTRL);
--
-- /*
-- * Enable PCIe link down reset, if link status changed from link up to
-- * link down, this will reset MAC control registers and configuration
-- * space.
-- */
-- writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
--
-- /* De-assert PHY, PE, PIPE, MAC and configuration reset */
-- val = readl(port->base + PCIE_RST_CTRL);
-- val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
-- PCIE_MAC_SRSTB | PCIE_CRSTB;
-- writel(val, port->base + PCIE_RST_CTRL);
--
-- /* Set up vendor ID and class code */
-- if (soc->need_fix_class_id) {
-- val = PCI_VENDOR_ID_MEDIATEK;
-- writew(val, port->base + PCIE_CONF_VEND_ID);
--
-- val = PCI_CLASS_BRIDGE_HOST;
-- writew(val, port->base + PCIE_CONF_CLASS_ID);
-- }
--
-- /* 100ms timeout value should be enough for Gen1/2 training */
-- err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
-- !!(val & PCIE_PORT_LINKUP_V2), 20,
-- 100 * USEC_PER_MSEC);
-- if (err)
-- return -ETIMEDOUT;
--
-- /* Set INTx mask */
-- val = readl(port->base + PCIE_INT_MASK);
-- val &= ~INTX_MASK;
-- writel(val, port->base + PCIE_INT_MASK);
--
-- /* Set AHB to PCIe translation windows */
-- size = mem->end - mem->start;
-- val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
-- writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
--
-- val = upper_32_bits(mem->start);
-- writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
--
-- /* Set PCIe to AXI translation memory space.*/
-- val = fls(0xffffffff) | WIN_ENABLE;
-- writel(val, port->base + PCIE_AXI_WINDOW0);
--
-- return 0;
--}
--
- static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
- {
- struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
-@@ -601,6 +533,27 @@ static void mtk_pcie_enable_msi(struct m
+@@ -532,6 +533,27 @@ static void mtk_pcie_enable_msi(struct m
writel(val, port->base + PCIE_INT_MASK);
}
static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
-@@ -630,6 +583,7 @@ static int mtk_pcie_init_irq_domain(stru
+@@ -561,6 +583,7 @@ static int mtk_pcie_init_irq_domain(stru
port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
&intx_domain_ops, port);
if (!port->irq_domain) {
dev_err(dev, "failed to get INTx IRQ domain\n");
return -ENODEV;
-@@ -639,8 +593,6 @@ static int mtk_pcie_init_irq_domain(stru
- ret = mtk_pcie_allocate_msi_domains(port);
- if (ret)
- return ret;
--
-- mtk_pcie_enable_msi(port);
- }
-
- return 0;
-@@ -693,7 +645,7 @@ static int mtk_pcie_setup_irq(struct mtk
+@@ -622,7 +645,7 @@ static int mtk_pcie_setup_irq(struct mtk
struct mtk_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
err = mtk_pcie_init_irq_domain(port, node);
if (err) {
-@@ -701,8 +653,81 @@ static int mtk_pcie_setup_irq(struct mtk
+@@ -630,8 +653,9 @@ static int mtk_pcie_setup_irq(struct mtk
return err;
}
+ port->irq = platform_get_irq(pdev, port->slot);
+ irq_set_chained_handler_and_data(port->irq,
+ mtk_pcie_intr_handler, port);
-+
-+ return 0;
-+}
-+
-+static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
-+{
-+ struct mtk_pcie *pcie = port->pcie;
-+ struct resource *mem = &pcie->mem;
-+ const struct mtk_pcie_soc *soc = port->pcie->soc;
-+ u32 val;
-+ size_t size;
-+ int err;
-+
-+ /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
-+ if (pcie->base) {
-+ val = readl(pcie->base + PCIE_SYS_CFG_V2);
-+ val |= PCIE_CSR_LTSSM_EN(port->slot) |
-+ PCIE_CSR_ASPM_L1_EN(port->slot);
-+ writel(val, pcie->base + PCIE_SYS_CFG_V2);
-+ }
-+
-+ /* Assert all reset signals */
-+ writel(0, port->base + PCIE_RST_CTRL);
-+
-+ /*
-+ * Enable PCIe link down reset, if link status changed from link up to
-+ * link down, this will reset MAC control registers and configuration
-+ * space.
-+ */
-+ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
-+
-+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
-+ val = readl(port->base + PCIE_RST_CTRL);
-+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
-+ PCIE_MAC_SRSTB | PCIE_CRSTB;
-+ writel(val, port->base + PCIE_RST_CTRL);
-+
-+ /* Set up vendor ID and class code */
-+ if (soc->need_fix_class_id) {
-+ val = PCI_VENDOR_ID_MEDIATEK;
-+ writew(val, port->base + PCIE_CONF_VEND_ID);
-+
-+ val = PCI_CLASS_BRIDGE_PCI;
-+ writew(val, port->base + PCIE_CONF_CLASS_ID);
-+ }
-+
-+ /* 100ms timeout value should be enough for Gen1/2 training */
-+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
-+ !!(val & PCIE_PORT_LINKUP_V2), 20,
-+ 100 * USEC_PER_MSEC);
-+ if (err)
-+ return -ETIMEDOUT;
-+
-+ /* Set INTx mask */
-+ val = readl(port->base + PCIE_INT_MASK);
-+ val &= ~INTX_MASK;
-+ writel(val, port->base + PCIE_INT_MASK);
-+
-+ if (IS_ENABLED(CONFIG_PCI_MSI))
-+ mtk_pcie_enable_msi(port);
-+
-+ /* Set AHB to PCIe translation windows */
-+ size = mem->end - mem->start;
-+ val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
-+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
-+
-+ val = upper_32_bits(mem->start);
-+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
-+
-+ /* Set PCIe to AXI translation memory space.*/
-+ val = fls(0xffffffff) | WIN_ENABLE;
-+ writel(val, port->base + PCIE_AXI_WINDOW0);
return 0;
}
-@@ -903,49 +928,29 @@ static int mtk_pcie_parse_port(struct mt
+@@ -904,49 +928,29 @@ static int mtk_pcie_parse_port(struct mt
/* sys_ck might be divided into the following parts in some chips */
snprintf(name, sizeof(name), "ahb_ck%d", slot);
snprintf(name, sizeof(name), "pcie-rst%d", slot);
port->reset = devm_reset_control_get_optional_exclusive(dev, name);
-@@ -998,10 +1003,8 @@ static int mtk_pcie_subsys_powerup(struc
+@@ -999,10 +1003,8 @@ static int mtk_pcie_subsys_powerup(struc
pcie->free_ck = NULL;
}
/* enable top level clock */
err = clk_prepare_enable(pcie->free_ck);
-@@ -1013,10 +1016,8 @@ static int mtk_pcie_subsys_powerup(struc
+@@ -1014,10 +1016,8 @@ static int mtk_pcie_subsys_powerup(struc
return 0;
err_free_ck:
return err;
}
-@@ -1122,8 +1122,6 @@
+@@ -1122,36 +1122,6 @@ static int mtk_pcie_request_resources(st
return err;
err = devm_pci_remap_iospace(dev, &pcie->pio, pcie->io.start);
- if (err)
- return err;
-
- return 0;
- }
-@@ -1127,34 +1128,6 @@ static int mtk_pcie_request_resources(st
- return 0;
- }
-
+-
+- return 0;
+-}
+-
-static int mtk_pcie_register_host(struct pci_host_bridge *host)
-{
- struct mtk_pcie *pcie = pci_host_bridge_priv(host);
- pcie_bus_configure_settings(child);
-
- pci_bus_add_devices(host->bus);
--
-- return 0;
--}
--
- static int mtk_pcie_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-@@ -1181,7 +1154,14 @@ static int mtk_pcie_probe(struct platfor
+
+ return 0;
+ }
+@@ -1182,7 +1152,14 @@ static int mtk_pcie_probe(struct platfor
if (err)
goto put_resources;
if (err)
goto put_resources;
-@@ -1194,6 +1174,80 @@ put_resources:
+@@ -1195,6 +1172,80 @@ put_resources:
return err;
}
static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
.ops = &mtk_pcie_ops,
.startup = mtk_pcie_startup_port,
-@@ -1222,10 +1276,13 @@ static const struct of_device_id mtk_pci
+@@ -1223,10 +1274,13 @@ static const struct of_device_id mtk_pci
static struct platform_driver mtk_pcie_driver = {
.probe = mtk_pcie_probe,
projects / openwrt / openwrt.git / blobdiff