ramips: fix RavPower WD03 SoC dtsi include

[openwrt/openwrt.git] / target / linux / ramips / dts / TL-WR902ACV3.dts

diff --git a/target/linux/ramips/dts/TL-WR902ACV3.dts b/target/linux/ramips/dts/TL-WR902ACV3.dts
index bfdc03b1b33604ceadab7ca13e98496bd8ea419d..b7860412861af71ce85c19160a19f7258faab480 100644 (file)
--- a/target/linux/ramips/dts/TL-WR902ACV3.dts
+++ b/target/linux/ramips/dts/TL-WR902ACV3.dts
@@ -9,10 +9,15 @@
        compatible = "tplink,tl-wr902ac-v3", "mediatek,mt7628an-soc";
        model = "TP-Link TL-WR902AC v3";
 
+       aliases {
+               led-boot = &led_power;
+               led-failsafe = &led_power;
+               led-running = &led_power;
+               led-upgrade = &led_power;
+       };
+
        gpio-keys-polled {
                compatible = "gpio-keys-polled";
-               #address-cells = <1>;
-               #size-cells = <0>;
                poll-interval = <20>;
 
                reset {
@@ -48,7 +53,7 @@
                        gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
                };
 
-               power {
+               led_power: power {
                        label = "tl-wr902ac-v3:green:power";
                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                };
@@ -56,6 +61,8 @@
                usb {
                        label = "tl-wr902ac-v3:green:usb";
                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+                       trigger-sources = <&ohci_port1>, <&ehci_port1>;
+                       linux,default-trigger = "usbport";
                };
 
                wan {
@@ -94,15 +101,14 @@
 
 &pcie {
        status = "okay";
+};
 
-       pcie-bridge {
-               mt76@1,0 {
-                       reg = <0x0000 0 0 0 0>;
-                       device_type = "pci";
-                       mediatek,mtd-eeprom = <&factory 0x28000>;
-                       ieee80211-freq-limit = <5000000 6000000>;
-                       mtd-mac-address = <&factory 0xf100>;
-                       mtd-mac-address-increment = <(-1)>;
-               };
+&pcie0 {
+       mt76@0,0 {
+               reg = <0x0000 0 0 0 0>;
+               mediatek,mtd-eeprom = <&factory 0x28000>;
+               ieee80211-freq-limit = <5000000 6000000>;
+               mtd-mac-address = <&factory 0xf100>;
+               mtd-mac-address-increment = <(-1)>;
        };
 };