ramips: Fix GB-PC1 cpuclock again
[openwrt/openwrt.git] / target / linux / ramips / dts / VR500.dts
index 8b5d98fa697485629a16db774f7a57f086bdb42e..776cc2ac5cb7915b0bc67fd3bef1d746c7d126ca 100644 (file)
@@ -2,10 +2,11 @@
 
 #include "mt7621.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
 / {
-       compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
+       compatible = "planex,vr500", "mediatek,mt7621-soc";
        model = "Planex VR500";
 
        memory@0 {
@@ -22,7 +23,7 @@
 
                power {
                        label = "vr500:green:power";
-                       gpios = <&gpio1 13 1>;
+                       gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
                };
        };
 
 
                reset {
                        label = "reset";
-                       gpios = <&gpio1 15 1>;
+                       gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
                        linux,code = <KEY_RESTART>;
                };
        };
 };
 
-&xhci {
-       status = "okay";
-};
-
 &spi0 {
        status = "okay";
 
@@ -52,8 +49,8 @@
                #size-cells = <1>;
                compatible = "jedec,spi-nor";
                reg = <0>;
-               linux,modalias = "m25p80";
                spi-max-frequency = <10000000>;
+               m25p,chunked-io = <32>;
 
                partition@0 {
                        label = "u-boot";
@@ -88,7 +85,3 @@
                };
        };
 };
-
-&pcie {
-       status = "disabled";
-};