#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/mtd/partitions/uimage.h>
/ {
gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
-
- switch_high {
- label = "switch high";
- gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- };
-
- switch_off {
- label = "switch off";
- gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- };
};
leds {
compatible = "gpio-leds";
led_power: power {
- label = "green:power";
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
};
lan {
- label = "green:lan";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
};
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1radio";
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0radio";
- };
-
wps {
- label = "green:wps";
+ function = LED_FUNCTION_WPS;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
-
- crossband {
- label = "green:crossband";
- gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
- };
};
};
read-only;
};
- factory: partition@40000 {
+ partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x200>;
+ };
+
+ eeprom_factory_8000: eeprom@8000 {
+ reg = <0x8000 0x200>;
+ };
+
+ macaddr_factory_4: macaddr@4 {
+ compatible = "mac-base";
+ reg = <0x4 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
};
partition@50000 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
- mtd-mac-address = <&factory 0x4>;
-
- mediatek,mdio-mode = <1>;
+ nvmem-cells = <&macaddr_factory_4 0>;
+ nvmem-cell-names = "mac-address";
phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
phy-reset-duration = <30>;
};
};
+&gsw {
+ mediatek,ephy-base = /bits/ 8 <8>;
+};
+
&wmac {
- ralink,mtd-eeprom = <&factory 0x0>;
+ nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_4 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
&pcie {
&pcie0 {
wifi@0,0 {
reg = <0x0000 0 0 0 0>;
- mediatek,mtd-eeprom = <&factory 0x8000>;
- mediatek,2ghz = <0>;
+ ieee80211-freq-limit = <5000000 6000000>;
+ nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_4 2>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
};