bootargs = "console=ttyS0,57600";
};
+#ifdef DTS_LEGACY
pll: pll {
compatible = "mediatek,mt7621-pll", "syscon";
#clock-cells = <1>;
clock-output-names = "cpu", "bus";
};
+#endif
sysclock: sysclock {
#clock-cells = <0>;
clock-frequency = <50000000>;
};
- palmbus: palmbus@1E000000 {
+ palmbus: palmbus@1e000000 {
compatible = "palmbus";
- reg = <0x1E000000 0x100000>;
- ranges = <0x0 0x1E000000 0x0FFFFF>;
+ reg = <0x1e000000 0x100000>;
+ ranges = <0x0 0x1e000000 0x0fffff>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "mtk,mt7621-sysc";
+ sysc: syscon@0 {
+#ifdef DTS_LEGACY
+ compatible = "mtk,mt7621-sysc", "syscon";
+#else
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ #clock-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
+#endif
reg = <0x0 0x100>;
};
#interrupt-cells = <2>;
compatible = "mediatek,mt7621-gpio";
gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 95>;
interrupt-controller;
reg = <0x600 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
};
- memc: memc@5000 {
- compatible = "mtk,mt7621-memc";
+ memc: syscon@5000 {
+#ifdef DTS_LEGACY
+ compatible = "mtk,mt7621-memc", "syscon";
+#else
+ compatible = "mediatek,mt7621-memc", "syscon";
+#endif
reg = <0x5000 0x1000>;
};
- cpc: cpc@1fbf0000 {
- compatible = "mtk,mt7621-cpc";
- reg = <0x1fbf0000 0x8000>;
- };
-
- mc: mc@1fbf8000 {
- compatible = "mtk,mt7621-mc";
- reg = <0x1fbf8000 0x8000>;
- };
-
uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
+#ifdef DTS_LEGACY
clocks = <&pll MT7621_CLK_BUS>;
+#else
+ clocks = <&sysc MT7621_CLK_BUS>;
+#endif
resets = <&rstctrl 18>;
reset-names = "spi";
reset-names = "dma";
interrupt-parent = <&gic>;
- interrupts = <0 13 4>;
+ interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <16>;
reset-names = "hsdma";
interrupt-parent = <&gic>;
- interrupts = <0 11 4>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <1>;
#clock-cells = <1>;
};
- sdhci: sdhci@1E130000 {
+ sdhci: sdhci@1e130000 {
status = "disabled";
compatible = "ralink,mt7620-sdhci";
- reg = <0x1E130000 0x4000>;
+ reg = <0x1e130000 0x4000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&sdhci_pins>;
};
- xhci: xhci@1E1C0000 {
+ xhci: xhci@1e1c0000 {
#address-cells = <1>;
#size-cells = <0>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+#ifdef DTS_LEGACY
clocks = <&pll MT7621_CLK_CPU>;
+#else
+ clocks = <&sysc MT7621_CLK_CPU>;
+#endif
};
};
clock-frequency = <125000000>;
};
+ cpc: cpc@1fbf0000 {
+ compatible = "mti,mips-cpc";
+ reg = <0x1fbf0000 0x8000>;
+ };
+
+ mc: mc@1fbf8000 {
+ compatible = "mti,mips-cdmm";
+ reg = <0x1fbf8000 0x8000>;
+ };
+
nand: nand@1e003000 {
status = "disabled";
clock-names = "nfi_clk";
};
- ethsys: syscon@1e000000 {
- compatible = "mediatek,mt7621-ethsys",
- "syscon";
- reg = <0x1e000000 0x1000>;
- #clock-cells = <1>;
- };
-
ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
+#ifdef DTS_LEGACY
clocks = <&sysclock>;
clock-names = "ethif";
+#else
+ clocks = <&sysc MT7621_CLK_FE>,
+ <&sysc MT7621_CLK_ETH>;
+ clock-names = "fe", "ethif";
+#endif
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 6 &rstctrl 23>;
+ resets = <&rstctrl 6>, <&rstctrl 23>;
reset-names = "fe", "eth";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
- mediatek,ethsys = <ðsys>;
+ mediatek,ethsys = <&sysc>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
- phy-mode = "rgmii-rxid";
+ phy-mode = "rgmii";
};
mdio: mdio-bus {
switch0: switch@1f {
compatible = "mediatek,mt7621";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0x1f>;
mediatek,mcm;
resets = <&rstctrl 2>;
reset-names = "mcm";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
port@0 {
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
+ pause;
};
};
};
};
};
- gsw: gsw@1e110000 {
- compatible = "mediatek,mt7621-gsw";
- reg = <0x1e110000 0x8000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
- };
-
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e140000 0x100 /* host-pci bridge registers */
- 0x1e142000 0x100 /* pcie port 0 RC control registers */
- 0x1e143000 0x100 /* pcie port 1 RC control registers */
- 0x1e144000 0x100>; /* pcie port 2 RC control registers */
+ reg = <0x1e140000 0x100>, /* host-pci bridge registers */
+ <0x1e142000 0x100>, /* pcie port 0 RC control registers */
+ <0x1e143000 0x100>, /* pcie port 1 RC control registers */
+ <0x1e144000 0x100>; /* pcie port 2 RC control registers */
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- bus-range = <0 255>;
- ranges = <
- 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
- 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
- >;
+#ifdef DTS_LEGACY
+ ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
+ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
+#else
+ ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
+ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
+#endif
+
+ status = "disabled";
+#ifdef DTS_LEGACY
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
+ resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
reset-names = "pcie0", "pcie1", "pcie2";
- clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
+ clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
phy-names = "pcie-phy0", "pcie-phy2";
+#else
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xF800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+#endif
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ device_type = "pci";
ranges;
- bus-range = <0x00 0xff>;
+#ifndef DTS_LEGACY
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstctrl 24>;
+ clocks = <&sysc MT7621_CLK_PCIE0>;
+ phys = <&pcie0_phy 1>;
+ phy-names = "pcie-phy0";
+#endif
};
pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ device_type = "pci";
ranges;
- bus-range = <0x00 0xff>;
+#ifndef DTS_LEGACY
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstctrl 25>;
+ clocks = <&sysc MT7621_CLK_PCIE1>;
+ phys = <&pcie0_phy 1>;
+ phy-names = "pcie-phy1";
+#endif
};
pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ device_type = "pci";
ranges;
- bus-range = <0x00 0xff>;
+#ifndef DTS_LEGACY
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstctrl 26>;
+ clocks = <&sysc MT7621_CLK_PCIE2>;
+ phys = <&pcie2_phy 0>;
+ phy-names = "pcie-phy2";
+#endif
};
};
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+#ifndef DTS_LEGACY
+ clocks = <&sysc MT7621_CLK_XTAL>;
+#endif
#phy-cells = <1>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
+#ifndef DTS_LEGACY
+ clocks = <&sysc MT7621_CLK_XTAL>;
+#endif
#phy-cells = <1>;
};
};
projects / openwrt / openwrt.git / blobdiff