clock-frequency = <50000000>;
};
- palmbus@1E000000 {
+ palmbus: palmbus@1E000000 {
compatible = "palmbus";
reg = <0x1E000000 0x100000>;
ranges = <0x0 0x1E000000 0x0FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
- sysc@0 {
+ sysc: sysc@0 {
compatible = "mtk,mt7621-sysc";
reg = <0x0 0x100>;
};
- wdt@100 {
+ wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
};
};
};
- memc@5000 {
+ i2c: i2c@900 {
+ compatible = "mediatek,mt7621-i2c";
+ reg = <0x900 0x100>;
+
+ clocks = <&sysclock>;
+
+ resets = <&rstctrl 16>;
+ reset-names = "i2c";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ };
+
+ i2s: i2s@a00 {
+ compatible = "mediatek,mt7621-i2s";
+ reg = <0xa00 0x100>;
+
+ clocks = <&sysclock>;
+
+ resets = <&rstctrl 17>;
+ reset-names = "i2s";
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
+
+ txdma-req = <2>;
+ rxdma-req = <3>;
+
+ dmas = <&gdma 4>,
+ <&gdma 6>;
+ dma-names = "tx", "rx";
+
+ status = "disabled";
+ };
+
+ memc: memc@5000 {
compatible = "mtk,mt7621-memc";
reg = <0x300 0x100>;
};
- cpc@1fbf0000 {
+ cpc: cpc@1fbf0000 {
compatible = "mtk,mt7621-cpc";
reg = <0x1fbf0000 0x8000>;
};
- mc@1fbf8000 {
+ mc: mc@1fbf8000 {
compatible = "mtk,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
reg = <0xc00 0x100>;
clocks = <&sysclock>;
+ clock-frequency = <50000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
- spi@b00 {
+ spi0: spi@b00 {
status = "okay";
compatible = "ralink,mt7621-spi";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
- reg = <0 0>;
+ reg = <0>;
spi-max-frequency = <10000000>;
m25p,chunked-io = <32>;
};
};
+
+ gdma: gdma@2800 {
+ compatible = "ralink,rt3883-gdma";
+ reg = <0x2800 0x800>;
+
+ resets = <&rstctrl 14>;
+ reset-names = "dma";
+
+ interrupt-parent = <&gic>;
+ interrupts = <0 13 4>;
+
+ #dma-cells = <1>;
+ #dma-channels = <16>;
+ #dma-requests = <16>;
+
+ status = "disabled";
+ };
+
+ hsdma: hsdma@7000 {
+ compatible = "mediatek,mt7621-hsdma";
+ reg = <0x7000 0x1000>;
+
+ resets = <&rstctrl 5>;
+ reset-names = "hsdma";
+
+ interrupt-parent = <&gic>;
+ interrupts = <0 11 4>;
+
+ #dma-cells = <1>;
+ #dma-channels = <1>;
+ #dma-requests = <1>;
+
+ status = "disabled";
+ };
};
- pinctrl {
+ pinctrl: pinctrl {
compatible = "ralink,rt2880-pinmux";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinctrl0 {
};
- spi_pins: spi {
- spi {
- ralink,group = "spi";
- ralink,function = "spi";
- };
- };
-
i2c_pins: i2c {
i2c {
ralink,group = "i2c";
};
};
+ spi_pins: spi {
+ spi {
+ ralink,group = "spi";
+ ralink,function = "spi";
+ };
+ };
+
uart1_pins: uart1 {
uart1 {
ralink,group = "uart1";
#reset-cells = <1>;
};
- sdhci@1E130000 {
+ clkctrl: clkctrl {
+ compatible = "ralink,rt2880-clock";
+ #clock-cells = <1>;
+ };
+
+ sdhci: sdhci@1E130000 {
compatible = "ralink,mt7620-sdhci";
- reg = <0x1E130000 4000>;
+ reg = <0x1E130000 0x4000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
};
- xhci@1E1C0000 {
+ xhci: xhci@1E1C0000 {
status = "okay";
compatible = "mediatek,mt8173-xhci";
};
};
- nand@1e003000 {
+ nand: nand@1e003000 {
status = "disabled";
compatible = "mtk,mt7621-nand";
#size-cells = <1>;
};
- ethernet@1e100000 {
+ ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
- reg = <0x1e100000 10000>;
+ reg = <0x1e100000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
gsw: gsw@1e110000 {
compatible = "mediatek,mt7621-gsw";
- reg = <0x1e110000 8000>;
+ reg = <0x1e110000 0x8000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
};
- pcie@1e140000 {
+ pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
reg = <0x1e140000 0x100
0x1e142000 0x100>;
status = "okay";
+ resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
+ reset-names = "pcie0", "pcie1", "pcie2";
+ clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
+ clock-names = "pcie0", "pcie1", "pcie2";
+
pcie0 {
reg = <0x0000 0 0 0 0>;