#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
-#define SYSTEM_CONFIG_CPUCLK_SHIFT 18
-#define SYSTEM_CONFIG_CPUCLK_MASK 0x1
-#define SYSTEM_CONFIG_CPUCLK_320 0x0
-#define SYSTEM_CONFIG_CPUCLK_384 0x1
-#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT 2
-#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK 0x3
-#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL 0
-#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT 1
-#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX 2
+#define RT305X_SYSCFG_CPUCLK_SHIFT 18
+#define RT305X_SYSCFG_CPUCLK_MASK 0x1
+#define RT305X_SYSCFG_CPUCLK_LOW 0x0
+#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
+#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3
+#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0
+#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1
+#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2
#define RT305X_GPIO_MODE_I2C BIT(0)
#define RT305X_GPIO_MODE_SPI BIT(1)