ralink: fix pcie reset

[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch

diff --git a/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
index 91f5feac89b91e053cdecaddaa774af0d84c0bcd..bea6a46098083794013b83b2639fbfc4ffd96c04 100644 (file)
--- a/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
+++ b/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
@@ -13,8 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 Index: linux-3.14.18/arch/mips/pci/Makefile
 ===================================================================
---- linux-3.14.18.orig/arch/mips/pci/Makefile  2014-11-13 15:45:37.323344081 +0100
-+++ linux-3.14.18/arch/mips/pci/Makefile       2014-11-13 15:45:37.331344390 +0100
+--- linux-3.14.18.orig/arch/mips/pci/Makefile  2014-11-17 16:02:34.009553392 +0100
++++ linux-3.14.18/arch/mips/pci/Makefile       2014-11-17 16:02:34.017553694 +0100
 @@ -42,6 +42,7 @@
  obj-$(CONFIG_LANTIQ)          += fixup-lantiq.o
  obj-$(CONFIG_PCI_LANTIQ)      += pci-lantiq.o ops-lantiq.o
@@ -26,8 +26,8 @@ Index: linux-3.14.18/arch/mips/pci/Makefile
 Index: linux-3.14.18/arch/mips/pci/pci-mt7620.c
 ===================================================================
 --- /dev/null  1970-01-01 00:00:00.000000000 +0000
-+++ linux-3.14.18/arch/mips/pci/pci-mt7620.c   2014-11-13 18:20:27.961225097 +0100
-@@ -0,0 +1,395 @@
++++ linux-3.14.18/arch/mips/pci/pci-mt7620.c   2014-11-17 16:09:52.814075085 +0100
+@@ -0,0 +1,396 @@
 +/*
 + *  Ralink MT7620A SoC PCI support
 + *
@@ -247,11 +247,12 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620.c
 +      /* PCIE: Elastic buffer control */
 +      pcie_phy(0x68, 0xB4);
 +
++      pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
++
 +      reset_control_assert(rstpcie0);
 +
 +      rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 +      rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
-+      rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
 +
 +      reset_control_deassert(rstpcie0);
 +      rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
@@ -425,8 +426,8 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620.c
 +arch_initcall(mt7620_pci_init);
 Index: linux-3.14.18/arch/mips/ralink/Kconfig
 ===================================================================
---- linux-3.14.18.orig/arch/mips/ralink/Kconfig        2014-11-13 15:45:37.323344081 +0100
-+++ linux-3.14.18/arch/mips/ralink/Kconfig     2014-11-13 15:45:37.331344390 +0100
+--- linux-3.14.18.orig/arch/mips/ralink/Kconfig        2014-11-17 16:02:34.009553392 +0100
++++ linux-3.14.18/arch/mips/ralink/Kconfig     2014-11-17 16:02:34.021553845 +0100
 @@ -39,6 +39,7 @@
                bool "MT7620/8"
                select USB_ARCH_HAS_OHCI
@@ -437,8 +438,8 @@ Index: linux-3.14.18/arch/mips/ralink/Kconfig
                bool "MT7621"
 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h
 ===================================================================
---- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/mt7620.h      2014-11-13 15:45:37.311343619 +0100
-+++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h   2014-11-13 18:20:31.721370073 +0100
+--- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/mt7620.h      2014-11-17 16:02:33.993552790 +0100
++++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h   2014-11-17 16:10:00.002345398 +0100
 @@ -19,6 +19,7 @@
        MT762X_SOC_MT7620N,
        MT762X_SOC_MT7628AN,