Some u-boot versions for QCA955x change the delays based on the link speed
during boot. This usually breaks the support of other linkspeeds when
OpenWrt is booted. It also conflicts with the
at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own
values in QCA955X_GMAC_REG_ETH_CFG.
The default RGMII values from the Atheros u-boot are currently used to
preset the existing mach files. These may have to be adjusted for boards
using different values but which are not currently set them explicitely in
OpenWrt.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Christian Beier <cb@shoutrlabs.com>
Cc: Chris R Blake <chrisrblake93@gmail.com>
Cc: Benjamin Berg <benjamin@sipsolutions.net>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
Cc: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Dirk Neukirchen <dirkneukirchen@web.de>
Cc: Christian Mehlis <christian@m3hlis.de>
Cc: Luka Perkov <luka@openwrt.org>
Cc: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 49029
19 files changed:
-void __init ath79_setup_qca955x_eth_cfg(u32 mask)
+void __init ath79_setup_qca955x_eth_cfg(u32 mask,
+ unsigned int rxd, unsigned int rxdv,
+ unsigned int txd, unsigned int txe)
{
void __iomem *base;
u32 t, m;
{
void __iomem *base;
u32 t, m;
QCA955X_ETH_CFG_RMII_GE0 |
QCA955X_ETH_CFG_MII_CNTL_SPEED |
QCA955X_ETH_CFG_RMII_GE0_MASTER;
QCA955X_ETH_CFG_RMII_GE0 |
QCA955X_ETH_CFG_MII_CNTL_SPEED |
QCA955X_ETH_CFG_RMII_GE0_MASTER;
+ m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+ t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
void ath79_setup_ar934x_eth_cfg(u32 mask);
void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
void ath79_setup_ar934x_eth_cfg(u32 mask);
void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
-void ath79_setup_qca955x_eth_cfg(u32 mask);
+void ath79_setup_qca955x_eth_cfg(u32 mask, unsigned int rxd, unsigned int rxdv,
+ unsigned int txd, unsigned int txe);
#endif /* _ATH79_DEV_ETH_H */
#endif /* _ATH79_DEV_ETH_H */
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(0, 0x0);
ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(f9k1115v2_mdio0_info,
ARRAY_SIZE(f9k1115v2_mdio0_info));
mdiobus_register_board_info(f9k1115v2_mdio0_info,
ARRAY_SIZE(f9k1115v2_mdio0_info));
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + F9K1115V2_WAN_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + F9K1115V2_WAN_MAC_OFFSET, 0);
ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
ath79_register_pci();
ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
ath79_register_pci();
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
res = mr18_extract_sgmii_res_cal();
if (res >= 0) {
/* Setup SoC Eth Config */
res = mr18_extract_sgmii_res_cal();
if (res >= 0) {
/* Setup SoC Eth Config */
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN |
- (3 << QCA955X_ETH_CFG_RXD_DELAY_SHIFT) |
- (3 << QCA955X_ETH_CFG_RDV_DELAY_SHIFT));
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0,
+ 0);
/* MDIO Interface */
ath79_register_mdio(0, 0x0);
/* MDIO Interface */
ath79_register_mdio(0, 0x0);
}
pdata->use_eeprom = true;
}
pdata->use_eeprom = true;
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(0, 0x0);
ARRAY_SIZE(tew_823dru_mdio0_info));
ath79_register_mdio(0, 0x0);
ARRAY_SIZE(tew_823dru_mdio0_info));
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ARRAY_SIZE(wzr_450hp2_mdio0_info));
ath79_register_mdio(0, 0x0);
ARRAY_SIZE(wzr_450hp2_mdio0_info));
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
+
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
-+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
++ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_mdio(0, 0x0);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_mdio(0, 0x0);
+
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
+
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
-+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
++ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_mdio(0, 0x0);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_mdio(0, 0x0);