-+static int bcma_pcie2_allow_gen2_rc(struct bcma_device *bdev)
-+{
-+ u32 vendorid, devid, chipid, chiprev;
-+ u32 val, bar;
-+ void __iomem *base;
-+ int allow = 1;
-+
-+ /* Read PCI vendor/device ID's */
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x0);
-+ val = bcma_read32(bdev, SOC_PCIE_CFG_DATA);
-+ vendorid = val & 0xffff;
-+ devid = val >> 16;
-+ if (vendorid == PCI_VENDOR_ID_BROADCOM &&
-+ (devid == BCMA_CHIP_ID_BCM4360 || devid == BCM4360_D11AC_ID ||
-+ devid == BCM4360_D11AC2G_ID || devid == BCM4360_D11AC5G_ID ||
-+ devid == BCM4352_D11AC_ID || devid == BCM4352_D11AC2G_ID ||
-+ devid == BCM4352_D11AC5G_ID)) {
-+ /* Config BAR0 */
-+ bar = bdev->addr_s[0];
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x10);
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, bar);
-+ /* Config BAR0 window to access chipc */
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x80);
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, SI_ENUM_BASE);
-+
-+ /* Enable memory resource */
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x4);
-+ val = bcma_read32(bdev, SOC_PCIE_CFG_DATA);
-+ val |= PCI_COMMAND_MEMORY;
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, val);
-+ /* Enable memory and bus master */
-+ bcma_write32(bdev, SOC_PCIE_HDR_OFF + 4, 0x6);
-+
-+ /* Read CHIP ID */
-+ base = ioremap(bar, 0x1000);
-+ val = __raw_readl(base);
-+ iounmap(base);
-+ chipid = val & 0xffff;
-+ chiprev = (val >> 16) & 0xf;
-+ if ((chipid == BCMA_CHIP_ID_BCM4360 ||
-+ chipid == BCMA_CHIP_ID_BCM43460 ||
-+ chipid == BCMA_CHIP_ID_BCM4352) && (chiprev < 3))
-+ allow = 0;
-+ }
-+ return allow;
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_CLASS_DEVICE, 2);
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_MEMORY_BASE, 2);
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_MEMORY_LIMIT, 2);
++ return 0;