+- case 43225:
+- break;
+ default:
+- pr_err("Workarounds unknown for device 0x%04X\n",
+- bus->chipinfo.id);
++ pr_debug("Workarounds unknown or not needed for device 0x%04X\n",
++ bus->chipinfo.id);
+ }
+ }
+
+@@ -174,12 +158,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+ bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
+ BCMA_CC_PMU_CTL_NOILPONW);
+
+- if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
+- pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
+-
+- bcma_pmu_pll_init(cc);
+ bcma_pmu_resources_init(cc);
+- bcma_pmu_swreg_init(cc);
+ bcma_pmu_workarounds(cc);
+ }
+
+@@ -188,17 +167,17 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+ struct bcma_bus *bus = cc->core->bus;
+
+ switch (bus->chipinfo.id) {
+- case 0x4716:
+- case 0x4748:
+- case 47162:
+- case 0x4313:
+- case 0x5357:
+- case 0x4749:
+- case 53572:
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM4748:
++ case BCMA_CHIP_ID_BCM47162:
++ case BCMA_CHIP_ID_BCM4313:
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
++ case BCMA_CHIP_ID_BCM53572:
+ /* always 20Mhz */
+ return 20000 * 1000;
+- case 0x5356:
+- case 0x5300:
++ case BCMA_CHIP_ID_BCM5356:
++ case BCMA_CHIP_ID_BCM4706:
+ /* always 25Mhz */
+ return 25000 * 1000;
+ default:
+@@ -221,7 +200,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
+
+ BUG_ON(!m || m > 4);
+
+- if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
+ /* Detect failure in clock setting */
+ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
+ if (tmp & 0x40000)
+@@ -253,22 +233,22 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
+ struct bcma_bus *bus = cc->core->bus;
+
+ switch (bus->chipinfo.id) {
+- case 0x4716:
+- case 0x4748:
+- case 47162:
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM4748:
++ case BCMA_CHIP_ID_BCM47162:
+ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_SSB);
+- case 0x5356:
++ case BCMA_CHIP_ID_BCM5356:
+ return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_SSB);
+- case 0x5357:
+- case 0x4749:
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
+ return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_SSB);
+- case 0x5300:
++ case BCMA_CHIP_ID_BCM4706:
+ return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_SSB);
+- case 53572:
++ case BCMA_CHIP_ID_BCM53572:
+ return 75000000;
+ default:
+ pr_warn("No backplane clock specified for %04X device, "
+@@ -283,17 +263,17 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+ {
+ struct bcma_bus *bus = cc->core->bus;
+
+- if (bus->chipinfo.id == 53572)
++ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
+ return 300000000;
+
+ if (cc->pmu.rev >= 5) {
+ u32 pll;
+ switch (bus->chipinfo.id) {
+- case 0x5356:
++ case BCMA_CHIP_ID_BCM5356:
+ pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
+ break;
+- case 0x5357:
+- case 0x4749:
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
+ pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
+ break;
+ default:
+@@ -301,10 +281,190 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+ break;
+ }
+
+- /* TODO: if (bus->chipinfo.id == 0x5300)
++ /* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
+ return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
+ return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
+ }
+
+ return bcma_pmu_get_clockcontrol(cc);
+ }
++
++static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
++ u32 value)
++{
++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
++}
++
++void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
++{
++ u32 tmp = 0;
++ u8 phypll_offset = 0;
++ u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
++ u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
++ struct bcma_bus *bus = cc->core->bus;
++
++ switch (bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
++ case BCMA_CHIP_ID_BCM53572:
++ /* 5357[ab]0, 43236[ab]0, and 6362b0 */
++
++ /* BCM5357 needs to touch PLL1_PLLCTL[02],
++ so offset PLL0_PLLCTL[02] by 6 */
++ phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
++ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
++ bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
++
++ /* RMW only the P1 divider */
++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
++ BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
++ tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
++ tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
++ tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
++
++ /* RMW only the int feedback divider */
++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
++ BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
++ tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
++ tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
++ tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
++ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
++
++ tmp = 1 << 10;
++ break;
++
++ case BCMA_CHIP_ID_BCM4331:
++ case BCMA_CHIP_ID_BCM43431:
++ if (spuravoid == 2) {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11500014);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x0FC00a08);
++ } else if (spuravoid == 1) {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11500014);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x0F600a08);
++ } else {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11100014);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x03000a08);
++ }
++ tmp = 1 << 10;
++ break;
++
++ case BCMA_CHIP_ID_BCM43224:
++ case BCMA_CHIP_ID_BCM43225:
++ case BCMA_CHIP_ID_BCM43421:
++ if (spuravoid == 1) {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11500010);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
++ 0x000C0C06);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x0F600a08);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
++ 0x00000000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
++ 0x2001E920);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
++ 0x88888815);
++ } else {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11100010);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
++ 0x000c0c06);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x03000a08);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
++ 0x00000000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
++ 0x200005c0);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
++ 0x88888815);
++ }
++ tmp = 1 << 10;
++ break;
++
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM4748:
++ case BCMA_CHIP_ID_BCM47162:
++ if (spuravoid == 1) {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11500060);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
++ 0x080C0C06);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x0F600000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
++ 0x00000000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
++ 0x2001E924);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
++ 0x88888815);
++ } else {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11100060);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
++ 0x080c0c06);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x03000000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
++ 0x00000000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
++ 0x200005c0);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
++ 0x88888815);
++ }
++
++ tmp = 3 << 9;
++ break;
++
++ case BCMA_CHIP_ID_BCM43227:
++ case BCMA_CHIP_ID_BCM43228:
++ case BCMA_CHIP_ID_BCM43428:
++ /* LCNXN */
++ /* PLL Settings for spur avoidance on/off mode,
++ no on2 support for 43228A0 */
++ if (spuravoid == 1) {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x01100014);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
++ 0x040C0C06);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x03140A08);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
++ 0x00333333);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
++ 0x202C2820);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
++ 0x88888815);
++ } else {
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
++ 0x11100014);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
++ 0x040c0c06);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
++ 0x03000a08);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
++ 0x00000000);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
++ 0x200005c0);
++ bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
++ 0x88888815);
++ }
++ tmp = 1 << 10;
++ break;
++ default:
++ pr_err("unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
++ bus->chipinfo.id);
++ break;
++ }
++
++ tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
++ bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
++}
++EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
+--- a/drivers/bcma/driver_mips.c
++++ b/drivers/bcma/driver_mips.c
+@@ -22,15 +22,15 @@
+ /* The 47162a0 hangs when reading MIPS DMP registers registers */
+ static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
+ {
+- return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
+- dev->id.id == BCMA_CORE_MIPS_74K;
++ return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
++ dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
+ }
+
+ /* The 5357b0 hangs when reading USB20H DMP registers */
+ static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
+ {
+- return (dev->bus->chipinfo.id == 0x5357 ||
+- dev->bus->chipinfo.id == 0x4749) &&
++ return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
++ dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
+ dev->bus->chipinfo.pkg == 11 &&
+ dev->id.id == BCMA_CORE_USB20_HOST;
+ }