++ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
++ mdelay(100);
++
++ pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
++
++ pci_config_read(NULL, 0, 0x70c, 4, &val);
++ val &= ~(0xff) << 8;
++ val |= 0x50 << 8;
++ pci_config_write(NULL, 0, 0x70c, 4, val);
++
++ pci_config_read(NULL, 0, 0x70c, 4, &val);
++ dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
++
++ return 0;
++}
++
++static int mt7620_pci_probe(struct platform_device *pdev)
++{
++ struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ u32 val = 0;
++
++ rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
++ if (IS_ERR(rstpcie0))
++ return PTR_ERR(rstpcie0);
++
++ bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
++ if (!bridge_base)
++ return -ENOMEM;
++
++ pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
++ if (!pcie_base)
++ return -ENOMEM;
++
++ iomem_resource.start = 0;
++ iomem_resource.end = ~0;
++ ioport_resource.start = 0;
++ ioport_resource.end = ~0;
++
++ /* bring up the pci core */
++ switch (mt762x_soc) {
++ case MT762X_SOC_MT7620A:
++ if (mt7620_pci_hw_init(pdev))
++ return -1;
++ break;
++
++ case MT762X_SOC_MT7628AN:
++ if (mt7628_pci_hw_init(pdev))
++ return -1;
++ break;
++
++ default:
++ dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
++ return -1;
++ }
++ mdelay(50);
++
++ /* enable write access */