ar71xx: rename ethernet pdata->builtin_switch to use_flow_control
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h
index b18c20b6ddf8922812de3790a2622c33197a5785..5d03dcf2bd9fff11ca7d2f08786fdaa31c164661 100644 (file)
 #define AG71XX_TX_RING_SPLIT           512
 #define AG71XX_TX_RING_DS_PER_PKT      DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
                                                     AG71XX_TX_RING_SPLIT)
-#define AG71XX_TX_RING_SIZE_DEFAULT    48
-#define AG71XX_RX_RING_SIZE_DEFAULT    128
+#define AG71XX_TX_RING_SIZE_DEFAULT    128
+#define AG71XX_RX_RING_SIZE_DEFAULT    256
 
-#define AG71XX_TX_RING_SIZE_MAX                48
-#define AG71XX_RX_RING_SIZE_MAX                128
+#define AG71XX_TX_RING_SIZE_MAX                128
+#define AG71XX_RX_RING_SIZE_MAX                256
 
 #ifdef CONFIG_AG71XX_DEBUG
 #define DBG(fmt, args...)      pr_debug(fmt, ## args)
@@ -85,6 +85,9 @@ struct ag71xx_desc {
        u32     pad;
 } __attribute__((aligned(4)));
 
+#define AG71XX_DESC_SIZE       roundup(sizeof(struct ag71xx_desc), \
+                                       L1_CACHE_BYTES)
+
 struct ag71xx_buf {
        union {
                struct sk_buff  *skb;
@@ -102,10 +105,9 @@ struct ag71xx_ring {
        u8                      *descs_cpu;
        dma_addr_t              descs_dma;
        u16                     desc_split;
-       u16                     desc_size;
+       u16                     order;
        unsigned int            curr;
        unsigned int            dirty;
-       unsigned int            size;
 };
 
 struct ag71xx_mdio {
@@ -205,7 +207,13 @@ static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
 static inline struct ag71xx_desc *
 ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
 {
-       return (struct ag71xx_desc *) &ring->descs_cpu[idx * ring->desc_size];
+       return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];
+}
+
+static inline int
+ag71xx_ring_size_order(int size)
+{
+       return fls(size - 1);
 }
 
 /* Register offsets */