+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
--- /dev/null
+++ b/arch/mips/ar231x/pci.c
-@@ -0,0 +1,234 @@
+@@ -0,0 +1,233 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/types.h>
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
+ mb();
+
-+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
++ addr = (u32)configspace + (1 << (13 + dev)) + (func << 8) + where;
+ if (size == 1)
+ addr ^= 0x3;
+ else if (size == 2)
+ return config_access(devfn, where, size, &value, 1);
+}
+
-+struct pci_ops ar231x_pci_ops = {
++static struct pci_ops ar231x_pci_ops = {
+ .read = ar231x_pci_read,
+ .write = ar231x_pci_write,
+};
+ .flags = IORESOURCE_IO,
+};
+
-+struct pci_controller ar231x_pci_controller = {
++static struct pci_controller ar231x_pci_controller = {
+ .pci_ops = &ar231x_pci_ops,
+ .mem_resource = &ar231x_mem_resource,
+ .io_resource = &ar231x_io_resource,
+ return -ENODEV;
+
+ /* Remap PCI config space */
-+ configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT,
-+ 1*1024*1024);
++ configspace = (unsigned long)ioremap_nocache(AR2315_PCIEXT,
++ 1 * 1024 * 1024);
+ ar231x_pci_controller.io_map_base =
-+ (unsigned long) ioremap_nocache(AR2315_MEM_BASE +
++ (unsigned long)ioremap_nocache(AR2315_MEM_BASE +
+ AR2315_MEM_SIZE, AR2315_IO_SIZE);
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
+
+ msleep(20);
+
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
-+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
++ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
+
+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
-+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
++ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
-+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
-+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
++ AR2315_IF_PCI | AR2315_IF_PCI_HOST |
++ AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
++ AR2315_IF_PCI_CLK_SHIFT));
+
+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
-+ AR2315_PCIRST_LOW);
++ AR2315_PCIRST_LOW);
+ msleep(100);
+
+ /* Bring the PCI out of reset */
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
-+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
+
+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
-+ 0x1E | /* 1GB uncached */
-+ (1 << 5) | /* Enable uncached */
-+ (0x2 << 30) /* Base: 0x80000000 */
-+ );
++ 0x1E | /* 1GB uncached */
++ (1 << 5) | /* Enable uncached */
++ (0x2 << 30) /* Base: 0x80000000 */);
+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
+
+ msleep(500);
+arch_initcall(ar2315_pci_init);
--- a/arch/mips/ar231x/Kconfig
+++ b/arch/mips/ar231x/Kconfig
-@@ -14,3 +14,10 @@ config ATHEROS_AR2315
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
+@@ -7,3 +7,10 @@ config ATHEROS_AR2315
+ bool "Atheros 2315+ support"
+ depends on ATHEROS_AR231X
default y
+
+config ATHEROS_AR2315_PCI
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
+}
+
-+void ar2315_pci_irq(int irq)
++static void ar2315_pci_irq(int irq)
+{
+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
+ pci_abort_irq();