--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -545,6 +545,9 @@ static void vc4_hdmi_encoder_post_crtc_p
+@@ -546,6 +546,9 @@ static void vc4_hdmi_encoder_post_crtc_p
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
-@@ -849,9 +852,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -850,9 +853,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
* pixel clock, but HSM ends up being the limiting factor.
*/
hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
return;
}
-@@ -863,10 +866,12 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -864,10 +867,12 @@ static void vc4_hdmi_encoder_pre_crtc_co
* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
* at 300MHz.
*/
clk_disable_unprepare(vc4_hdmi->pixel_clock);
return;
}
-@@ -874,6 +879,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -875,6 +880,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
if (ret) {
DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);