#size-cells = <1>;
compatible = "brcm,bcm6348";
+ aliases {
+ pflash = &pflash;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "brcm,bmips3300", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
};
};
+ cpu_intc: interrupt-controller {
+ #address-cells = <0>;
+ compatible = "mti,cpu-interrupt-controller";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
memory { device_type = "memory"; reg = <0 0>; };
+ pflash: nor@1fc00000 {
+ compatible = "cfi-flash";
+ reg = <0x1fc00000 0x400000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
ubus@fff00000 {
#address-cells = <1>;
#size-cells = <1>;
+ ranges;
compatible = "simple-bus";
+
+ periph_intc: interrupt-controller@fffe000c {
+ compatible = "brcm,bcm6345-l1-intc";
+ reg = <0xfffe000c 0x8>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>;
+ };
+
+ ext_intc: interrupt-controller@fffe0014 {
+ compatible = "brcm,bcm6345-ext-intc";
+ reg = <0xfffe0014 0x4>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <3>, <4>, <5>, <6>;
+
+ brcm,field-width = <5>;
+ };
+
+ gpio1: gpio-controller@fffe0400 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0400 4>, <0xfffe0408 4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ngpios = <5>;
+
+ interrupt-parent = <&ext_intc>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>;
+ interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3";
+ };
+
+ gpio0: gpio-controller@fffe0404 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0404 4>, <0xfffe040c 4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
};