#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/io.h>
+#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
.size = SZ_128K,
.offset = SZ_256K,
}, {
- .name = "kernel",
- .size = SZ_2M,
+ .name = "firmware",
.offset = SZ_256K + SZ_128K,
- }, {
- .name = "rootfs",
- .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
- .offset = SZ_256K + SZ_128K + SZ_2M,
},
};
.size = SZ_256K,
.offset = SZ_256K,
}, {
- .name = "kernel",
- .size = SZ_1M + SZ_512K,
+ .name = "firmware",
.offset = SZ_512K,
- }, {
- .name = "rootfs",
- .size = SZ_16M - SZ_2M,
- .offset = SZ_2M,
},
};
static struct platform_device laguna_gpio_leds_device = {
.name = "leds-gpio",
- .id = -1,
+ .id = PLATFORM_DEVID_NONE,
.dev.platform_data = &laguna_gpio_leds_data,
};
.end = CNS3XXX_UART0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM
},{
- .start = CNS3XXX_UART2_BASE,
- .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
+ .start = CNS3XXX_UART1_BASE,
+ .end = CNS3XXX_UART1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM
},{
.start = CNS3XXX_UART2_BASE,
.resource = laguna_i2c_resource,
};
-static struct memory_accessor *at24_mem_acc;
+static struct nvmem_device *at24_nvmem;
-static void at24_setup(struct memory_accessor *mem_acc, void *context)
+static void at24_setup(struct nvmem_device *mem_acc, void *context)
{
char buf[16];
- at24_mem_acc = mem_acc;
+ at24_nvmem = mem_acc;
/* Read MAC addresses */
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
+ if (nvmem_device_read(at24_nvmem, 0x100, 6, buf) == 6)
memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
+ if (nvmem_device_read(at24_nvmem, 0x106, 6, buf) == 6)
memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
+ if (nvmem_device_read(at24_nvmem, 0x10C, 6, buf) == 6)
memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
+ if (nvmem_device_read(at24_nvmem, 0x112, 6, buf) == 6)
memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
/* Read out Model Information */
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
+ if (nvmem_device_read(at24_nvmem, 0x130, 16, buf) == 16)
memcpy(&laguna_info.model, buf, 16);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
+ if (nvmem_device_read(at24_nvmem, 0x140, 1, buf) == 1)
memcpy(&laguna_info.nor_flash_size, buf, 1);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
+ if (nvmem_device_read(at24_nvmem, 0x141, 1, buf) == 1)
memcpy(&laguna_info.spi_flash_size, buf, 1);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
+ if (nvmem_device_read(at24_nvmem, 0x142, 4, buf) == 4)
memcpy(&laguna_info.config_bitmap, buf, 4);
- if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
+ if (nvmem_device_read(at24_nvmem, 0x146, 4, buf) == 4)
memcpy(&laguna_info.config2_bitmap, buf, 4);
};
static struct platform_device laguna_watchdog = {
.name = "mpcore_wdt",
- .id = -1,
+ .id = PLATFORM_DEVID_NONE,
.num_resources = ARRAY_SIZE(laguna_watchdog_resources),
.resource = laguna_watchdog_resources,
};
static struct platform_device laguna_pps_device = {
.name = "pps-gpio",
- .id = -1,
+ .id = PLATFORM_DEVID_NONE,
.dev.platform_data = &laguna_pps_data,
};
{ 113, GPIOF_IN , "DIO5" },
};
+static struct gpio laguna_gpio_gw2386[] = {
+ { 0, GPIOF_IN , "*GPS_PPS" },
+ { 2, GPIOF_IN , "*USB_FAULT#" },
+ { 6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
+ { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
+ { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
+ { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
+ { 108, GPIOF_IN , "DIO0" },
+ { 109, GPIOF_IN , "DIO1" },
+ { 110, GPIOF_IN , "DIO2" },
+ { 111, GPIOF_IN , "DIO3" },
+ { 112, GPIOF_IN , "DIO4" },
+ { 113, GPIOF_IN , "DIO5" },
+};
+
static struct gpio laguna_gpio_gw2385[] = {
{ 0, GPIOF_IN , "*GSC_IRQ#" },
{ 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
u32 __iomem *reg;
clk = clk_register_fixed_rate(NULL, "cpu", NULL,
- CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+ CLK_IGNORE_UNUSED,
cns3xxx_cpu_clock() * (1000000 / 8));
clk_register_clkdev(clk, "cpu", NULL);
static void __init laguna_map_io(void)
{
cns3xxx_map_io();
- cns3xxx_pcie_iotable_init();
iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
laguna_early_serial_setup();
}
return ret;
}
-static int __init laguna_pcie_init(void)
+/* allow disabling of external isolated PCIe IRQs */
+static int cns3xxx_pciextirq = 1;
+static int __init cns3xxx_pciextirq_disable(char *s)
{
+ cns3xxx_pciextirq = 0;
+ return 1;
+}
+__setup("noextirq", cns3xxx_pciextirq_disable);
+
+static int __init laguna_pcie_init_irq(void)
+{
+ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
+ u32 reg = (__raw_readl(mem) >> 26) & 0xf;
+ int irqs[] = {
+ IRQ_CNS3XXX_EXTERNAL_PIN0,
+ IRQ_CNS3XXX_EXTERNAL_PIN1,
+ IRQ_CNS3XXX_EXTERNAL_PIN2,
+ 154,
+ };
+
if (!machine_is_gw2388())
return 0;
- return cns3xxx_pcie_init();
+ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
+ if (cns3xxx_pciextirq && reg != 1)
+ cns3xxx_pciextirq = 0;
+
+ if (cns3xxx_pciextirq) {
+ printk("laguna: using isolated PCI interrupts:"
+ " irq%d/irq%d/irq%d/irq%d\n",
+ irqs[0], irqs[1], irqs[2], irqs[3]);
+ cns3xxx_pcie_set_irqs(0, irqs);
+ } else {
+ printk("laguna: using shared PCI interrupts: irq%d\n",
+ IRQ_CNS3XXX_PCIE0_DEVICE);
+ }
+
+ return 0;
}
-subsys_initcall(laguna_pcie_init);
+subsys_initcall(laguna_pcie_init_irq);
static int __init laguna_model_setup(void)
{
printk("Running on Gateworks Laguna %s\n", laguna_info.model);
cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
NR_IRQS_CNS3XXX);
- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
- NR_IRQS_CNS3XXX + 32);
+
+ /*
+ * If pcie external interrupts are supported and desired
+ * configure IRQ types and configure pin function.
+ * Note that cns3xxx_pciextirq is enabled by default, but can be
+ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
+ * the baseboard model does not support this hardware feature.
+ */
+ if (cns3xxx_pciextirq) {
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
+ reg = __raw_readl(mem);
+ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
+ reg &= ~0x3c000000;
+ reg |= 0x38000000;
+ __raw_writel(reg, mem);
+
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
+
+ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
+ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
+ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
+ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
+ } else {
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
+ }
if (strncmp(laguna_info.model, "GW", 2) == 0) {
if (laguna_info.config_bitmap & ETH0_LOAD)
platform_device_register(&laguna_uart);
if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
- switch (laguna_info.nor_flash_size) {
- case 1:
- laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
- laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
- break;
- case 2:
- laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
- laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
- break;
- case 3:
- laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
- laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
- break;
- case 4:
- laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
- laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
- break;
- case 5:
- laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
- laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
- break;
- }
+ laguna_nor_partitions[2].size =
+ (SZ_4M << laguna_info.nor_flash_size) -
+ laguna_nor_partitions[2].offset;
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE +
+ laguna_nor_partitions[2].offset +
+ laguna_nor_partitions[2].size - 1;
platform_device_register(&laguna_nor_pdev);
}
if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
- switch (laguna_info.spi_flash_size) {
- case 1:
- laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
- break;
- case 2:
- laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
- break;
- case 3:
- laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
- break;
- case 4:
- laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
- break;
- case 5:
- laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
- break;
- }
+ laguna_spi_partitions[2].size =
+ (SZ_2M << laguna_info.spi_flash_size) -
+ laguna_spi_partitions[2].offset;
spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
}
laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
// configure LED's
laguna_gpio_leds_data.num_leds = 2;
+ } else if (strncmp(laguna_info.model, "GW2386", 6) == 0) {
+ // configure GPIO's
+ laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386));
+ // configure LED's
+ laguna_gpio_leds_data.num_leds = 2;
} else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
// configure GPIO's
laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
laguna_gpio_leds[3].name = "blue";
laguna_gpio_leds[3].active_low = 0,
laguna_gpio_leds_data.num_leds = 4;
- } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
+ } else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0)
+ || (strncmp(laguna_info.model, "GW2394", 6) == 0) )
+ {
// configure GPIO's
laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
// configure LED's
laguna_gpio_leds[0].gpio = 107;
laguna_gpio_leds[1].gpio = 106;
laguna_gpio_leds_data.num_leds = 2;
- } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
+ } else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0)
+ || (strncmp(laguna_info.model, "GW2393", 6) == 0) )
+ {
// configure GPIO's
laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
// configure LED's
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = laguna_init,
+ .init_late = cns3xxx_pcie_init_late,
.restart = cns3xxx_restart,
MACHINE_END
projects / openwrt / openwrt.git / blobdiff