++config MPCORE_WATCHDOG
++ tristate "MPcore watchdog"
++ depends on HAVE_ARM_TWD
++ select WATCHDOG_CORE
++ help
++ Watchdog timer embedded into the MPcore system
++
+ config HAVE_S3C2410_WATCHDOG
+ bool
+ help
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
+ obj-$(CONFIG_977_WATCHDOG) += wdt977.o
+ obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
+ obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
++obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
+ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
+ obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
+ obj-$(CONFIG_SAMA5D4_WATCHDOG) += sama5d4_wdt.o
+--- /dev/null
++++ b/drivers/watchdog/mpcore_wdt.c
+@@ -0,0 +1,117 @@
++/*
++ * Watchdog driver for ARM MPcore
++ *
++ * Copyright (C) 2017 Felix Fietkau <nbd@nbd.name>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <asm/smp_twd.h>
++
++static void __iomem *wdt_base;
++static int wdt_timeout = 60;
++
++static int mpcore_wdt_keepalive(struct watchdog_device *wdd)
++{
++ static int perturb;
++ u32 count;
++
++ count = ioread32(wdt_base + TWD_WDOG_COUNTER);
++ count = (~0U - count) * HZ / 5;
++ count /= 256; /* prescale */
++ count *= wdt_timeout;
++
++ /* Reload register needs a different value on each refresh */
++ count += perturb;
++ perturb = !perturb;
++
++ iowrite32(count, wdt_base + TWD_WDOG_LOAD);
++
++ return 0;
++}
++
++static int mpcore_wdt_start(struct watchdog_device *wdd)
++{
++ mpcore_wdt_keepalive(wdd);
++
++ /* prescale = 256, mode = 1, enable = 1 */
++ iowrite32(0x0000FF09, wdt_base + TWD_WDOG_CONTROL);
++
++ return 0;
++}
++
++static int mpcore_wdt_stop(struct watchdog_device *wdd)
++{
++ iowrite32(0x12345678, wdt_base + TWD_WDOG_DISABLE);
++ iowrite32(0x87654321, wdt_base + TWD_WDOG_DISABLE);
++ iowrite32(0x0, wdt_base + TWD_WDOG_CONTROL);
++
++ return 0;
++}
++
++static int mpcore_wdt_set_timeout(struct watchdog_device *wdd,
++ unsigned int timeout)
++{
++ mpcore_wdt_stop(wdd);
++ wdt_timeout = timeout;
++ mpcore_wdt_start(wdd);
++
++ return 0;
++}
++
++static const struct watchdog_info mpcore_wdt_info = {
++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++ .identity = "MPcore Watchdog",
++};
++
++static const struct watchdog_ops mpcore_wdt_ops = {
++ .owner = THIS_MODULE,
++ .start = mpcore_wdt_start,
++ .stop = mpcore_wdt_stop,
++ .ping = mpcore_wdt_keepalive,
++ .set_timeout = mpcore_wdt_set_timeout,
++};
++
++static struct watchdog_device mpcore_wdt = {
++ .info = &mpcore_wdt_info,
++ .ops = &mpcore_wdt_ops,
++ .min_timeout = 1,
++ .max_timeout = 65535,