struct net_device_ops ndo;
struct mutex reg_mutex;
int chip;
+ bool initialized;
+ bool port4_phy;
+ char buf[80];
+
+ bool init;
/* all fields below are cleared on reset */
bool vlan;
ar8216_mii_read(struct ar8216_priv *priv, int reg)
{
struct phy_device *phy = priv->phy;
+ struct mii_bus *bus = phy->bus;
u16 r1, r2, page;
u16 lo, hi;
split_addr((u32) reg, &r1, &r2, &page);
- phy->bus->write(phy->bus, 0x18, 0, page);
+
+ mutex_lock(&bus->mdio_lock);
+
+ bus->write(bus, 0x18, 0, page);
msleep(1); /* wait for the page switch to propagate */
- lo = phy->bus->read(phy->bus, 0x10 | r2, r1);
- hi = phy->bus->read(phy->bus, 0x10 | r2, r1 + 1);
+ lo = bus->read(bus, 0x10 | r2, r1);
+ hi = bus->read(bus, 0x10 | r2, r1 + 1);
+
+ mutex_unlock(&bus->mdio_lock);
return (hi << 16) | lo;
}
ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
{
struct phy_device *phy = priv->phy;
+ struct mii_bus *bus = phy->bus;
u16 r1, r2, r3;
u16 lo, hi;
split_addr((u32) reg, &r1, &r2, &r3);
- phy->bus->write(phy->bus, 0x18, 0, r3);
- msleep(1); /* wait for the page switch to propagate */
-
lo = val & 0xffff;
hi = (u16) (val >> 16);
- phy->bus->write(phy->bus, 0x10 | r2, r1 + 1, hi);
- phy->bus->write(phy->bus, 0x10 | r2, r1, lo);
+
+ mutex_lock(&bus->mdio_lock);
+
+ bus->write(bus, 0x18, 0, r3);
+ msleep(1); /* wait for the page switch to propagate */
+ bus->write(bus, 0x10 | r2, r1 + 1, hi);
+ bus->write(bus, 0x10 | r2, r1, lo);
+
+ mutex_unlock(&bus->mdio_lock);
}
static u32
switch (id) {
case 0x0101:
return AR8216;
+ case 0x0301:
+ return AR8236;
case 0x1000:
case 0x1001:
return AR8316;
"ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
(int)(id >> AR8216_CTRL_VERSION_S),
(int)(id & AR8216_CTRL_REVISION),
- priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 2),
- priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 3));
+ mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
+ mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
return UNKNOWN;
}
}
+static void
+ar8216_read_port_link(struct ar8216_priv *priv, int port,
+ struct switch_port_link *link)
+{
+ u32 status;
+ u32 speed;
+
+ memset(link, '\0', sizeof(*link));
+
+ status = priv->read(priv, AR8216_REG_PORT_STATUS(port));
+
+ link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
+ if (link->aneg) {
+ link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
+ if (!link->link)
+ return;
+ } else {
+ link->link = true;
+ }
+
+ link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
+ link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
+ link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
+
+ speed = (status & AR8216_PORT_STATUS_SPEED) >>
+ AR8216_PORT_STATUS_SPEED_S;
+
+ switch (speed) {
+ case AR8216_PORT_SPEED_10M:
+ link->speed = SWITCH_PORT_SPEED_10;
+ break;
+ case AR8216_PORT_SPEED_100M:
+ link->speed = SWITCH_PORT_SPEED_100;
+ break;
+ case AR8216_PORT_SPEED_1000M:
+ link->speed = SWITCH_PORT_SPEED_1000;
+ break;
+ default:
+ link->speed = SWITCH_PORT_SPEED_UNKNOWN;
+ break;
+ }
+}
+
static int
ar8216_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
return 0;
}
+static int
+ar8216_get_port_link(struct switch_dev *dev, int port,
+ struct switch_port_link *link)
+{
+ struct ar8216_priv *priv = to_ar8216(dev);
+
+ ar8216_read_port_link(priv, port, link);
+ return 0;
+}
static int
ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
{
int timeout = 20;
+ u32 t = 0;
- while ((priv->read(priv, reg) & mask) != val) {
- if (timeout-- <= 0) {
- printk(KERN_ERR "ar8216: timeout waiting for operation to complete\n");
- return 1;
- }
+ while (1) {
+ t = priv->read(priv, reg);
+ if ((t & mask) == val)
+ return 0;
+
+ if (timeout-- <= 0)
+ break;
+
+ udelay(10);
}
- return 0;
+
+ pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
+ (unsigned int) reg, t, mask, val);
+ return -ETIMEDOUT;
}
static void
priv->write(priv, AR8216_REG_VTU, op);
}
+static void
+ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
+ u32 members, u32 pvid)
+{
+ u32 header;
+
+ if (priv->vlan && port == AR8216_PORT_CPU && priv->chip == AR8216)
+ header = AR8216_PORT_CTRL_HEADER;
+ else
+ header = 0;
+
+ ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
+ AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
+ AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
+ AR8216_PORT_CTRL_LEARN | header |
+ (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
+ (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
+
+ ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
+ AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
+ AR8216_PORT_VLAN_DEFAULT_ID,
+ (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
+ (ingress << AR8216_PORT_VLAN_MODE_S) |
+ (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
+}
+
+static void
+ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
+ u32 members, u32 pvid)
+{
+ ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
+ AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
+ AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
+ AR8216_PORT_CTRL_LEARN |
+ (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
+ (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
+
+ ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
+ AR8236_PORT_VLAN_DEFAULT_ID,
+ (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
+
+ ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
+ AR8236_PORT_VLAN2_VLAN_MODE |
+ AR8236_PORT_VLAN2_MEMBER,
+ (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
+ (members << AR8236_PORT_VLAN2_MEMBER_S));
+}
+
static int
ar8216_hw_apply(struct switch_dev *dev)
{
ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
memset(portmask, 0, sizeof(portmask));
- if (priv->vlan) {
+ if (!priv->init) {
/* calculate the port destination masks and load vlans
* into the vlan translation unit */
for (j = 0; j < AR8X16_MAX_VLANS; j++) {
pvid = i;
}
- if (priv->vlan && (priv->vlan_tagged & (1 << i))) {
- egress = AR8216_OUT_ADD_VLAN;
+ if (priv->vlan) {
+ if (priv->vlan_tagged & (1 << i))
+ egress = AR8216_OUT_ADD_VLAN;
+ else
+ egress = AR8216_OUT_STRIP_VLAN;
} else {
- egress = AR8216_OUT_STRIP_VLAN;
+ egress = AR8216_OUT_KEEP;
}
if (priv->vlan) {
ingress = AR8216_IN_SECURE;
ingress = AR8216_IN_PORT_ONLY;
}
- ar8216_rmw(priv, AR8216_REG_PORT_CTRL(i),
- AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
- AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
- AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
- AR8216_PORT_CTRL_LEARN |
- (priv->vlan && i == AR8216_PORT_CPU && (priv->chip == AR8216) ?
- AR8216_PORT_CTRL_HEADER : 0) |
- (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
- (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
-
- ar8216_rmw(priv, AR8216_REG_PORT_VLAN(i),
- AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
- AR8216_PORT_VLAN_DEFAULT_ID,
- (portmask[i] << AR8216_PORT_VLAN_DEST_PORTS_S) |
- (ingress << AR8216_PORT_VLAN_MODE_S) |
- (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
+ if (priv->chip == AR8236)
+ ar8236_setup_port(priv, i, egress, ingress, portmask[i],
+ pvid);
+ else
+ ar8216_setup_port(priv, i, egress, ingress, portmask[i],
+ pvid);
}
mutex_unlock(&priv->reg_mutex);
return 0;
}
static int
-ar8316_hw_init(struct ar8216_priv *priv) {
+ar8236_hw_init(struct ar8216_priv *priv) {
static int initialized;
int i;
- u32 val;
struct mii_bus *bus;
if (initialized)
return 0;
+ /* Initialize the PHYs */
+ bus = priv->phy->bus;
+ for (i = 0; i < 5; i++) {
+ mdiobus_write(bus, i, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
+ ADVERTISE_PAUSE_ASYM);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+ msleep(1000);
+
+ initialized = true;
+ return 0;
+}
+
+static int
+ar8316_hw_init(struct ar8216_priv *priv) {
+ int i;
+ u32 val, newval;
+ struct mii_bus *bus;
+
val = priv->read(priv, 0x8);
if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
- /* value taken from Ubiquiti RouterStation Pro */
- if (val == 0x81461bea) {
- /* switch already intialized by bootloader */
- initialized = true;
- return 0;
+ if (priv->port4_phy) {
+ /* value taken from Ubiquiti RouterStation Pro */
+ newval = 0x81461bea;
+ printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
+ } else {
+ newval = 0x01261be2;
+ printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
}
- priv->write(priv, 0x8, 0x81461bea);
} else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
/* value taken from AVM Fritz!Box 7390 sources */
- if (val == 0x010e5b71) {
- /* switch already initialized by bootloader */
- initialized = true;
- return 0;
- }
- priv->write(priv, 0x8, 0x010e5b71);
+ newval = 0x010e5b71;
} else {
/* no known value for phy interface */
printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
return -EINVAL;
}
+ if (val == newval)
+ goto out;
+
+ priv->write(priv, 0x8, newval);
+
/* standard atheros magic */
priv->write(priv, 0x38, 0xc000050e);
/* Initialize the ports */
bus = priv->phy->bus;
for (i = 0; i < 5; i++) {
- if ((i == 4) &&
- priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
+ if ((i == 4) && priv->port4_phy &&
+ priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
/* work around for phy4 rgmii mode */
- bus->write(bus, i, MII_ATH_DBG_ADDR, 0x12);
- bus->write(bus, i, MII_ATH_DBG_DATA, 0x480c);
+ mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12);
+ mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c);
/* rx delay */
- bus->write(bus, i, MII_ATH_DBG_ADDR, 0x0);
- bus->write(bus, i, MII_ATH_DBG_DATA, 0x824e);
+ mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0);
+ mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e);
/* tx delay */
- bus->write(bus, i, MII_ATH_DBG_ADDR, 0x5);
- bus->write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
+ mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5);
+ mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
msleep(1000);
}
/* initialize the port itself */
- bus->write(bus, i, MII_ADVERTISE,
+ mdiobus_write(bus, i, MII_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
- bus->write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- bus->write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
msleep(1000);
}
- initialized = true;
+
+out:
+ priv->initialized = true;
return 0;
}
if (priv->chip == AR8216) {
ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8216_GCTRL_MTU, 1518 + 8 + 2);
- } else if (priv->chip == AR8316) {
+ } else if (priv->chip == AR8316 ||
+ priv->chip == AR8236) {
/* enable jumbo frames */
ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
.set_vlan_ports = ar8216_set_ports,
.apply_config = ar8216_hw_apply,
.reset_switch = ar8216_reset_switch,
+ .get_port_link = ar8216_get_port_link,
};
static int
ar8216_config_init(struct phy_device *pdev)
{
- struct ar8216_priv *priv;
+ struct ar8216_priv *priv = pdev->priv;
struct net_device *dev = pdev->attached_dev;
struct switch_dev *swdev;
int ret;
- priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
- if (priv == NULL)
- return -ENOMEM;
+ if (!priv) {
+ priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
+ if (priv == NULL)
+ return -ENOMEM;
+ }
priv->phy = pdev;
priv->chip = ar8216_id_chip(priv);
- if (pdev->addr == 0)
- printk(KERN_INFO "%s: AR%d switch driver attached.\n",
- pdev->attached_dev->name, priv->chip);
-
-
if (pdev->addr != 0) {
if (priv->chip == AR8316) {
pdev->supported |= SUPPORTED_1000baseT_Full;
pdev->advertising |= ADVERTISED_1000baseT_Full;
+
+ /* check if we're attaching to the switch twice */
+ pdev = pdev->bus->phy_map[0];
+ if (!pdev) {
+ kfree(priv);
+ return 0;
+ }
+
+ /* switch device has not been initialized, reuse priv */
+ if (!pdev->priv) {
+ priv->port4_phy = true;
+ pdev->priv = priv;
+ return 0;
+ }
+
+ kfree(priv);
+
+ /* switch device has been initialized, reinit */
+ priv = pdev->priv;
+ priv->dev.ports = (AR8216_NUM_PORTS - 1);
+ priv->initialized = false;
+ priv->port4_phy = true;
+ ar8316_hw_init(priv);
+ return 0;
}
+
kfree(priv);
return 0;
}
+ printk(KERN_INFO "%s: AR%d switch driver attached.\n",
+ pdev->attached_dev->name, priv->chip);
+
pdev->supported = priv->chip == AR8316 ?
SUPPORTED_1000baseT_Full : SUPPORTED_100baseT_Full;
pdev->advertising = pdev->supported;
swdev = &priv->dev;
swdev->cpu_port = AR8216_PORT_CPU;
swdev->ops = &ar8216_ops;
+ swdev->ports = AR8216_NUM_PORTS;
if (priv->chip == AR8316) {
swdev->name = "Atheros AR8316";
swdev->vlans = AR8X16_MAX_VLANS;
- /* port 5 connected to the other mac, therefore unusable */
- swdev->ports = (AR8216_NUM_PORTS - 1);
+
+ if (priv->port4_phy) {
+ /* port 5 connected to the other mac, therefore unusable */
+ swdev->ports = (AR8216_NUM_PORTS - 1);
+ }
+ } else if (priv->chip == AR8236) {
+ swdev->name = "Atheros AR8236";
+ swdev->vlans = AR8216_NUM_VLANS;
+ swdev->ports = AR8216_NUM_PORTS;
} else {
swdev->name = "Atheros AR8216";
swdev->vlans = AR8216_NUM_VLANS;
- swdev->ports = AR8216_NUM_PORTS;
}
if ((ret = register_switch(&priv->dev, pdev->attached_dev)) < 0) {
goto done;
}
+ priv->init = true;
+
if (priv->chip == AR8316) {
ret = ar8316_hw_init(priv);
if (ret) {
}
}
+ if (priv->chip == AR8236) {
+ ret = ar8236_hw_init(priv);
+ if (ret) {
+ kfree(priv);
+ goto done;
+ }
+ }
+
ret = ar8216_reset_switch(&priv->dev);
if (ret) {
kfree(priv);
dev->netdev_ops = &priv->ndo;
}
+ priv->init = false;
+
done:
return ret;
}
ar8216_read_status(struct phy_device *phydev)
{
struct ar8216_priv *priv = phydev->priv;
+ struct switch_port_link link;
int ret;
if (phydev->addr != 0) {
return genphy_read_status(phydev);
}
- phydev->speed = priv->chip == AR8316 ? SPEED_1000 : SPEED_100;
- phydev->duplex = DUPLEX_FULL;
- phydev->link = 1;
+ ar8216_read_port_link(priv, phydev->addr, &link);
+ phydev->link = !!link.link;
+ if (!phydev->link)
+ return 0;
+
+ switch (link.speed) {
+ case SWITCH_PORT_SPEED_10:
+ phydev->speed = SPEED_10;
+ break;
+ case SWITCH_PORT_SPEED_100:
+ phydev->speed = SPEED_100;
+ break;
+ case SWITCH_PORT_SPEED_1000:
+ phydev->speed = SPEED_1000;
+ break;
+ default:
+ phydev->speed = 0;
+ }
+ phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
/* flush the address translation unit */
mutex_lock(&priv->reg_mutex);
ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
-
if (!ret)
priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
- else
- ret = -ETIMEDOUT;
mutex_unlock(&priv->reg_mutex);
phydev->state = PHY_RUNNING;
static struct phy_driver ar8216_driver = {
.phy_id = 0x004d0000,
- .name = "Atheros AR8216/AR8316",
+ .name = "Atheros AR8216/AR8236/AR8316",
.phy_id_mask = 0xffff0000,
.features = PHY_BASIC_FEATURES,
.probe = ar8216_probe,
projects / openwrt / openwrt.git / blobdiff