generic: ar8216: add support for separated mdio bus for phy access

[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.h

diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h
index 321eeb79231fbf8a50296c01feb5208d9eacc5a1..0444bf7f2243bf5af8bfee3fa6ebb16cd57ed8c6 100644 (file)
--- a/target/linux/generic/files/drivers/net/phy/ar8216.h
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.h
@@ -52,6 +52,8 @@
 #define AR8216_REG_FLOOD_MASK          0x002C
 #define   AR8216_FM_UNI_DEST_PORTS     BITS(0, 6)
 #define   AR8216_FM_MULTI_DEST_PORTS   BITS(16, 6)
+#define   AR8229_FLOOD_MASK_MC_DP(_p)  BIT(16 + (_p))
+#define   AR8229_FLOOD_MASK_BC_DP(_p)  BIT(25 + (_p))
 #define   AR8236_FM_CPU_BROADCAST_EN   BIT(26)
 #define   AR8236_FM_CPU_BCAST_FWD_EN   BIT(25)
 
@@ -112,6 +114,7 @@
 
 #define AR8216_REG_ATU_FUNC2           0x0058
 #define   AR8216_ATU_PORTS             BITS(0, 6)
+#define   AR8216_ATU_PORTS_S           0
 #define   AR8216_ATU_PORT0             BIT(0)
 #define   AR8216_ATU_PORT1             BIT(1)
 #define   AR8216_ATU_PORT2             BIT(2)
@@ -126,6 +129,12 @@
 #define   AR8216_ATU_CTRL_AGE_TIME     BITS(0, 16)
 #define   AR8216_ATU_CTRL_AGE_TIME_S   0
 #define   AR8236_ATU_CTRL_RES          BIT(20)
+#define   AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
+
+#define AR8216_REG_TAG_PRIORITY        0x0070
+
+#define AR8216_REG_SERVICE_TAG         0x0074
+#define  AR8216_SERVICE_TAG_M          BITS(0, 16)
 
 #define AR8216_REG_MIB_FUNC            0x0080
 #define   AR8216_MIB_TIMER             BITS(0, 16)
@@ -141,6 +150,7 @@
 #define AR8216_REG_GLOBAL_CPUPORT              0x0078
 #define   AR8216_GLOBAL_CPUPORT_MIRROR_PORT    BITS(4, 4)
 #define   AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S  4
+#define   AR8216_GLOBAL_CPUPORT_EN             BIT(8)
 
 #define AR8216_PORT_OFFSET(_i)         (0x0100 * (_i + 1))
 #define AR8216_REG_PORT_STATUS(_i)     (AR8216_PORT_OFFSET(_i) + 0x0000)
@@ -236,6 +246,16 @@
 #define AR8216_STATS_TXDEFER           0x98
 #define AR8216_STATS_TXLATECOL         0x9c
 
+#define AR8229_REG_OPER_MODE0          0x04
+#define   AR8229_OPER_MODE0_MAC_GMII_EN        BIT(6)
+#define   AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
+
+#define AR8229_REG_OPER_MODE1          0x08
+#define   AR8229_REG_OPER_MODE1_PHY4_MII_EN    BIT(28)
+
+#define AR8229_REG_QM_CTRL             0x3c
+#define   AR8229_QM_CTRL_ARP_EN                BIT(15)
+
 #define AR8236_REG_PORT_VLAN(_i)       (AR8216_PORT_OFFSET((_i)) + 0x0008)
 #define   AR8236_PORT_VLAN_DEFAULT_ID  BITS(16, 12)
 #define   AR8236_PORT_VLAN_DEFAULT_ID_S        16
@@ -367,7 +387,7 @@ enum arl_op {
 };
 
 struct arl_entry {
-       u8 port;
+       u16 portmap;
        u8 mac[6];
 };
 
@@ -412,6 +432,9 @@ struct ar8xxx_chip {
        void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
                              u32 *status, enum arl_op op);
        int (*sw_hw_apply)(struct switch_dev *dev);
+       void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);
+       int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);
+       int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);
 
        const struct ar8xxx_mib_desc *mib_decs;
        unsigned num_mibs;
@@ -421,7 +444,9 @@ struct ar8xxx_chip {
 struct ar8xxx_priv {
        struct switch_dev dev;
        struct mii_bus *mii_bus;
+       struct mii_bus *sw_mii_bus;
        struct phy_device *phy;
+       struct device *pdev;
 
        int (*get_port_link)(unsigned port);
 
@@ -462,6 +487,7 @@ struct ar8xxx_priv {
        bool mirror_tx;
        int source_port;
        int monitor_port;
+       u8 port_vlan_prio[AR8X16_MAX_PORTS];
 };
 
 u32
@@ -475,6 +501,9 @@ ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
 u32
 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 
+void
+ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
+               u16 dbg_addr, u16 *dbg_data);
 void
 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
                     u16 dbg_addr, u16 dbg_data);
@@ -566,9 +595,6 @@ ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
                                   const struct switch_attr *attr,
                                   struct switch_val *val);
 int
-ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
-                       struct switch_port_stats *stats);
-int
 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 
 static inline struct ar8xxx_priv *