kernel: bump 4.14 to 4.14.48 for 18.06

[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.14 / 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch

diff --git a/target/linux/ipq806x/patches-4.14/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch b/target/linux/ipq806x/patches-4.14/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch
index 1b19d6fcc2e697768ed5d77eb99e89fbd8caaff1..92100481c878230debfd8f34e1ee0fc30a50a04a 100644 (file)
--- a/target/linux/ipq806x/patches-4.14/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch
+++ b/target/linux/ipq806x/patches-4.14/0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x.patch
@@ -16,7 +16,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
 @@ -83,6 +83,30 @@
  #define PCIE20_CAP_LINK_1                     (PCIE20_CAP + 0x14)
  #define PCIE_CAP_LINK1_VAL                    0x2FD7F
-
+ 
 +#define PCIE20_CAP_LINKCTRLSTATUS             (PCIE20_CAP + 0x10)
 +
 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0               0x818
@@ -42,12 +42,12 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
 +#define MSM_PCIE_DEV_CFG_ADDR                 0x01000000
 +
  #define PCIE20_PARF_Q2A_FLUSH                 0x1AC
-
+ 
  #define PCIE20_MISC_CONTROL_1_REG             0x8BC
-@@ -251,6 +275,57 @@
-       writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
+@@ -251,6 +275,57 @@ static void qcom_pcie_2_1_0_ltssm_enable
+       writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
  }
-
+ 
 +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
 +{
 +      struct pcie_port *pp = &pcie->pci->pp;
@@ -101,14 +101,14 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
 +
  static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
  {
-       struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
-@@ -465,6 +538,9 @@
-       writel(CFG_BRIDGE_SB_INIT,
-              pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
-
+       struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+@@ -465,6 +540,9 @@ static int qcom_pcie_init_2_1_0(struct q
+       writel(CFG_BRIDGE_SB_INIT,
+              pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
+ 
 +      qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
 +      qcom_pcie_prog_viewport_mem2_outbound(pcie);
 +
-       return 0;
-
+       return 0;
+ 
  err_deassert_ahb: