--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -131,6 +131,14 @@
-
+
#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
-
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
+#define PCIE20_DEV_CAS 0x78
+#define PCIE20_MPS(x) __set(x, 7, 5)
+
struct qcom_pcie_resources_2_1_0 {
- struct clk *iface_clk;
- struct clk *core_clk;
-@@ -1472,6 +1480,35 @@
- return 0;
+ struct clk *iface_clk;
+ struct clk *core_clk;
+@@ -1472,6 +1480,35 @@ static int qcom_pcie_probe(struct platfo
+ return 0;
}
-
+
+static void qcom_pcie_fixup_final(struct pci_dev *dev)
+{
+ int cap, err;
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
+
static const struct of_device_id qcom_pcie_match[] = {
- { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
- { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
+ { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },