kernel: bump 4.14 to 4.14.48 for 18.06
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.14 / 0071-8-pcie-qcom-Fixed-pcie_phy_clk-branch-issue.patch
index 74f666dd5db2a2e94759246cd7a94c923252d32b..88bd7730c1f402255c6cddf14675759b45a132de 100644 (file)
@@ -38,54 +38,54 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
 
 --- a/drivers/pci/dwc/pcie-qcom.c
 +++ b/drivers/pci/dwc/pcie-qcom.c
-@@ -407,6 +407,7 @@
+@@ -407,6 +407,7 @@ static void qcom_pcie_deinit_2_1_0(struc
  {
-       struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
-
+       struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 +      clk_disable_unprepare(res->phy_clk);
-       reset_control_assert(res->pci_reset);
-       reset_control_assert(res->axi_reset);
-       reset_control_assert(res->ahb_reset);
-@@ -415,7 +415,6 @@
-       reset_control_assert(res->ext_reset);
-       clk_disable_unprepare(res->iface_clk);
-       clk_disable_unprepare(res->core_clk);
+       reset_control_assert(res->pci_reset);
+       reset_control_assert(res->axi_reset);
+       reset_control_assert(res->ahb_reset);
+@@ -415,7 +416,6 @@ static void qcom_pcie_deinit_2_1_0(struc
+       reset_control_assert(res->ext_reset);
+       clk_disable_unprepare(res->iface_clk);
+       clk_disable_unprepare(res->core_clk);
 -      clk_disable_unprepare(res->phy_clk);
-       clk_disable_unprepare(res->aux_clk);
-       clk_disable_unprepare(res->ref_clk);
-       regulator_disable(res->vdda);
-@@ -472,12 +472,6 @@
-               goto err_clk_core;
-       }
-
+       clk_disable_unprepare(res->aux_clk);
+       clk_disable_unprepare(res->ref_clk);
+       regulator_disable(res->vdda);
+@@ -472,12 +472,6 @@ static int qcom_pcie_init_2_1_0(struct q
+               goto err_clk_core;
+       }
 -      ret = clk_prepare_enable(res->phy_clk);
 -      if (ret) {
 -              dev_err(dev, "cannot prepare/enable phy clock\n");
 -              goto err_clk_phy;
 -      }
 -
-       ret = clk_prepare_enable(res->aux_clk);
-       if (ret) {
-               dev_err(dev, "cannot prepare/enable aux clock\n");
-@@ -541,6 +535,12 @@
-               return ret;
-       }
-
+       ret = clk_prepare_enable(res->aux_clk);
+       if (ret) {
+               dev_err(dev, "cannot prepare/enable aux clock\n");
+@@ -541,6 +535,12 @@ static int qcom_pcie_init_2_1_0(struct q
+               return ret;
+       }
 +      ret = clk_prepare_enable(res->phy_clk);
 +      if (ret) {
 +              dev_err(dev, "cannot prepare/enable phy clock\n");
 +              goto err_deassert_ahb;
 +      }
 +
-       /* wait for clock acquisition */
-       usleep_range(1000, 1500);
-       if (pcie->force_gen1) {
-@@ -566,8 +566,6 @@
+       /* wait for clock acquisition */
+       usleep_range(1000, 1500);
+       if (pcie->force_gen1) {
+@@ -566,8 +566,6 @@ err_deassert_ahb:
  err_clk_ref:
-       clk_disable_unprepare(res->aux_clk);
+       clk_disable_unprepare(res->aux_clk);
  err_clk_aux:
 -      clk_disable_unprepare(res->phy_clk);
 -err_clk_phy:
-       clk_disable_unprepare(res->core_clk);
+       clk_disable_unprepare(res->core_clk);
  err_clk_core:
-       clk_disable_unprepare(res->iface_clk);
+       clk_disable_unprepare(res->iface_clk);