enum pci_barno {
BAR_0,
BAR_1,
-@@ -92,6 +103,7 @@ struct pci_endpoint_test {
- void __iomem *bar[6];
- struct completion irq_raised;
- int last_irq;
-+ int num_irqs;
- /* mutex to protect the ioctls */
- struct mutex mutex;
- struct miscdevice miscdev;
-@@ -102,7 +114,7 @@ struct pci_endpoint_test {
+@@ -103,7 +114,7 @@ struct pci_endpoint_test {
struct pci_endpoint_test_data {
enum pci_barno test_reg_bar;
size_t alignment;
};
static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
-@@ -146,6 +158,100 @@ static irqreturn_t pci_endpoint_test_irq
+@@ -147,6 +158,100 @@ static irqreturn_t pci_endpoint_test_irq
return IRQ_HANDLED;
}
static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
enum pci_barno barno)
{
-@@ -178,6 +284,9 @@ static bool pci_endpoint_test_legacy_irq
+@@ -179,6 +284,9 @@ static bool pci_endpoint_test_legacy_irq
{
u32 val;
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
COMMAND_RAISE_LEGACY_IRQ);
val = wait_for_completion_timeout(&test->irq_raised,
-@@ -189,20 +298,24 @@ static bool pci_endpoint_test_legacy_irq
+@@ -190,20 +298,24 @@ static bool pci_endpoint_test_legacy_irq
}
static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
return true;
return false;
-@@ -226,10 +339,18 @@ static bool pci_endpoint_test_copy(struc
- u32 src_crc32;
- u32 dst_crc32;
+@@ -230,10 +342,18 @@ static bool pci_endpoint_test_copy(struc
+ if (size > SIZE_MAX - alignment)
+ goto err;
+ if (size > SIZE_MAX - alignment)
+ goto err;
ret = false;
goto err;
}
-@@ -255,7 +376,7 @@ static bool pci_endpoint_test_copy(struc
+@@ -259,7 +379,7 @@ static bool pci_endpoint_test_copy(struc
orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
&orig_dst_phys_addr, GFP_KERNEL);
if (!orig_dst_addr) {
ret = false;
goto err_orig_src_addr;
}
-@@ -277,8 +398,10 @@ static bool pci_endpoint_test_copy(struc
+@@ -281,8 +401,10 @@ static bool pci_endpoint_test_copy(struc
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
size);
wait_for_completion(&test->irq_raised);
-@@ -311,10 +434,18 @@ static bool pci_endpoint_test_write(stru
- size_t alignment = test->alignment;
- u32 crc32;
+@@ -318,10 +440,18 @@ static bool pci_endpoint_test_write(stru
+ if (size > SIZE_MAX - alignment)
+ goto err;
+ if (size > SIZE_MAX - alignment)
+ goto err;
ret = false;
goto err;
}
-@@ -341,8 +472,10 @@ static bool pci_endpoint_test_write(stru
+@@ -348,8 +478,10 @@ static bool pci_endpoint_test_write(stru
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
wait_for_completion(&test->irq_raised);
-@@ -369,10 +502,18 @@ static bool pci_endpoint_test_read(struc
- size_t alignment = test->alignment;
- u32 crc32;
+@@ -379,10 +511,18 @@ static bool pci_endpoint_test_read(struc
+ if (size > SIZE_MAX - alignment)
+ goto err;
+ if (size > SIZE_MAX - alignment)
+ goto err;
ret = false;
goto err;
}
-@@ -393,8 +534,10 @@ static bool pci_endpoint_test_read(struc
+@@ -403,8 +543,10 @@ static bool pci_endpoint_test_read(struc
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
wait_for_completion(&test->irq_raised);
-@@ -407,6 +550,38 @@ err:
+@@ -417,6 +559,38 @@ err:
return ret;
}
static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
-@@ -426,7 +601,8 @@ static long pci_endpoint_test_ioctl(stru
+@@ -436,7 +610,8 @@ static long pci_endpoint_test_ioctl(stru
ret = pci_endpoint_test_legacy_irq(test);
break;
case PCITEST_MSI:
break;
case PCITEST_WRITE:
ret = pci_endpoint_test_write(test, arg);
-@@ -437,6 +613,12 @@ static long pci_endpoint_test_ioctl(stru
+@@ -447,6 +622,12 @@ static long pci_endpoint_test_ioctl(stru
case PCITEST_COPY:
ret = pci_endpoint_test_copy(test, arg);
break;
}
ret:
-@@ -452,9 +634,7 @@ static const struct file_operations pci_
+@@ -462,9 +643,7 @@ static const struct file_operations pci_
static int pci_endpoint_test_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int id;
char name[20];
enum pci_barno bar;
-@@ -476,12 +656,15 @@ static int pci_endpoint_test_probe(struc
+@@ -486,12 +665,15 @@ static int pci_endpoint_test_probe(struc
test->alignment = 0;
test->pdev = pdev;
}
init_completion(&test->irq_raised);
-@@ -501,35 +684,21 @@ static int pci_endpoint_test_probe(struc
+@@ -511,36 +693,21 @@ static int pci_endpoint_test_probe(struc
pci_set_master(pdev);
- irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
- if (irq < 0)
- dev_err(dev, "failed to get MSI interrupts\n");
+- test->num_irqs = irq;
- }
+ if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
+ goto err_disable_irq;
}
test->base = test->bar[test_reg_bar];
-@@ -545,24 +714,31 @@ static int pci_endpoint_test_probe(struc
+@@ -556,24 +723,31 @@ static int pci_endpoint_test_probe(struc
id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
if (id < 0) {
err = id;
err_ida_remove:
ida_simple_remove(&pci_endpoint_test_ida, id);
-@@ -571,9 +747,10 @@ err_iounmap:
- if (test->bar[bar])
+@@ -583,11 +757,13 @@ err_iounmap:
pci_iounmap(pdev, test->bar[bar]);
}
+
+- for (i = 0; i < irq; i++)
+- devm_free_irq(dev, pdev->irq + i, test);
+ pci_endpoint_test_release_irq(test);
--err_disable_msi:
-- pci_disable_msi(pdev);
+ err_disable_msi:
+ pci_disable_msi(pdev);
++
+err_disable_irq:
+ pci_endpoint_test_free_irq_vectors(test);
pci_release_regions(pdev);
err_disable_pdev:
-@@ -595,12 +772,16 @@ static void pci_endpoint_test_remove(str
+@@ -610,14 +786,15 @@ static void pci_endpoint_test_remove(str
return;
misc_deregister(&test->miscdev);
if (test->bar[bar])
pci_iounmap(pdev, test->bar[bar]);
}
+- for (i = 0; i < test->num_irqs; i++)
+- devm_free_irq(&pdev->dev, pdev->irq + i, test);
- pci_disable_msi(pdev);
+
+ pci_endpoint_test_release_irq(test);
+ pci_endpoint_test_free_irq_vectors(test);
-+
pci_release_regions(pdev);
pci_disable_device(pdev);
}
-@@ -608,6 +789,7 @@ static void pci_endpoint_test_remove(str
+@@ -625,6 +802,7 @@ static void pci_endpoint_test_remove(str
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
-@@ -338,15 +338,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
+@@ -339,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
return IRQ_HANDLED;
}
struct pci_epf_header *hdr)
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
-@@ -74,8 +106,7 @@ static int dw_pcie_ep_inbound_atu(struct
- u32 free_win;
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
-- free_win = find_first_zero_bit(&ep->ib_window_map,
-- sizeof(ep->ib_window_map));
-+ free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
- if (free_win >= ep->num_ib_windows) {
- dev_err(pci->dev, "no free inbound window\n");
- return -EINVAL;
-@@ -89,7 +120,7 @@ static int dw_pcie_ep_inbound_atu(struct
- }
-
- ep->bar_to_atu[bar] = free_win;
-- set_bit(free_win, &ep->ib_window_map);
-+ set_bit(free_win, ep->ib_window_map);
-
- return 0;
- }
-@@ -100,8 +131,7 @@ static int dw_pcie_ep_outbound_atu(struc
- u32 free_win;
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
-- free_win = find_first_zero_bit(&ep->ob_window_map,
-- sizeof(ep->ob_window_map));
-+ free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
- if (free_win >= ep->num_ob_windows) {
- dev_err(pci->dev, "no free outbound window\n");
- return -EINVAL;
-@@ -110,30 +140,35 @@ static int dw_pcie_ep_outbound_atu(struc
- dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
- phys_addr, pci_addr, size);
-
-- set_bit(free_win, &ep->ob_window_map);
-+ set_bit(free_win, ep->ob_window_map);
- ep->outbound_addr[free_win] = phys_addr;
-
+@@ -114,24 +146,29 @@ static int dw_pcie_ep_outbound_atu(struc
return 0;
}
-static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
+static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
-+ struct pci_epf_bar *epf_bar)
++ struct pci_epf_bar *epf_bar)
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
-- clear_bit(atu_index, &ep->ib_window_map);
-+ clear_bit(atu_index, ep->ib_window_map);
+ clear_bit(atu_index, ep->ib_window_map);
}
-static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
- dma_addr_t bar_phys, size_t size, int flags)
+static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
-+ struct pci_epf_bar *epf_bar)
++ struct pci_epf_bar *epf_bar)
{
int ret;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
enum dw_pcie_as_type as_type;
u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
-@@ -142,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
+@@ -140,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
else
as_type = DW_PCIE_AS_IO;
dw_pcie_dbi_ro_wr_dis(pci);
return 0;
-@@ -169,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
+@@ -167,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
return -EINVAL;
}
{
int ret;
u32 atu_index;
-@@ -181,10 +224,11 @@ static void dw_pcie_ep_unmap_addr(struct
- return;
-
- dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
-- clear_bit(atu_index, &ep->ob_window_map);
-+ clear_bit(atu_index, ep->ob_window_map);
+@@ -182,8 +227,9 @@ static void dw_pcie_ep_unmap_addr(struct
+ clear_bit(atu_index, ep->ob_window_map);
}
-static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
+- u64 pci_addr, size_t size)
+static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
-+ phys_addr_t addr,
- u64 pci_addr, size_t size)
++ phys_addr_t addr,
++ u64 pci_addr, size_t size)
{
int ret;
-@@ -200,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+@@ -198,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
return 0;
}
-static int dw_pcie_ep_get_msi(struct pci_epc *epc)
+static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
- {
-- int val;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
++{
++ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
++ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msi_cap)
+ return -EINVAL;
-
-- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
-- if (!(val & MSI_CAP_MSI_EN_MASK))
++
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSI_FLAGS_ENABLE))
- return -EINVAL;
-
-- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
++ return -EINVAL;
++
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
+
- return val;
- }
-
--static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
++ return val;
++}
++
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
- {
-- int val;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
++{
++ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
++ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msi_cap)
+ return -EINVAL;
-
-- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
-- val &= ~MSI_CAP_MMC_MASK;
-- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
++
+ reg = ep->msi_cap + PCI_MSI_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSI_FLAGS_QMASK;
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
- dw_pcie_dbi_ro_wr_en(pci);
-- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
++ dw_pcie_dbi_ro_wr_en(pci);
+ dw_pcie_writew_dbi(pci, reg, val);
- dw_pcie_dbi_ro_wr_dis(pci);
-
- return 0;
- }
-
--static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
-- enum pci_epc_irq_type type, u8 interrupt_num)
++ dw_pcie_dbi_ro_wr_dis(pci);
++
++ return 0;
++}
++
+static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
-+{
-+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
-+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ {
+- int val;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
+
+ if (!ep->msix_cap)
+ return -EINVAL;
-+
+
+- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+- if (!(val & MSI_CAP_MSI_EN_MASK))
+ reg = ep->msix_cap + PCI_MSIX_FLAGS;
+ val = dw_pcie_readw_dbi(pci, reg);
+ if (!(val & PCI_MSIX_FLAGS_ENABLE))
-+ return -EINVAL;
-+
+ return -EINVAL;
+
+- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
+ val &= PCI_MSIX_FLAGS_QSIZE;
+
-+ return val;
-+}
-+
+ return val;
+ }
+
+-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
+static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
-+{
-+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
-+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ {
+- int val;
+ struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ u32 val, reg;
-+
+
+- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+- val &= ~MSI_CAP_MMC_MASK;
+- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
+ if (!ep->msix_cap)
+ return -EINVAL;
+
+ val = dw_pcie_readw_dbi(pci, reg);
+ val &= ~PCI_MSIX_FLAGS_QSIZE;
+ val |= interrupts;
-+ dw_pcie_dbi_ro_wr_en(pci);
+ dw_pcie_dbi_ro_wr_en(pci);
+- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
+ dw_pcie_writew_dbi(pci, reg, val);
-+ dw_pcie_dbi_ro_wr_dis(pci);
-+
-+ return 0;
-+}
-+
+ dw_pcie_dbi_ro_wr_dis(pci);
+
+ return 0;
+ }
+
+-static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
+- enum pci_epc_irq_type type, u8 interrupt_num)
+static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
+ enum pci_epc_irq_type type, u16 interrupt_num)
{
}
static void dw_pcie_ep_stop(struct pci_epc *epc)
-@@ -271,15 +363,130 @@ static const struct pci_epc_ops epc_ops
+@@ -269,15 +363,130 @@ static const struct pci_epc_ops epc_ops
.unmap_addr = dw_pcie_ep_unmap_addr,
.set_msi = dw_pcie_ep_set_msi,
.get_msi = dw_pcie_ep_get_msi,
pci_epc_mem_exit(epc);
}
-@@ -293,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
+@@ -291,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
struct device_node *np = dev->of_node;
if (!pci->dbi_base || !pci->dbi_base2) {
return -EINVAL;
}
-@@ -302,12 +509,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
- dev_err(dev, "unable to read *num-ib-windows* property\n");
- return ret;
- }
-+ if (ep->num_ib_windows > MAX_IATU_IN) {
-+ dev_err(dev, "invalid *num-ib-windows*\n");
-+ return -EINVAL;
-+ }
-
- ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
- if (ret < 0) {
- dev_err(dev, "unable to read *num-ob-windows* property\n");
- return ret;
- }
-+ if (ep->num_ob_windows > MAX_IATU_OUT) {
-+ dev_err(dev, "invalid *num-ob-windows*\n");
-+ return -EINVAL;
-+ }
-+
-+ ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
-+ BITS_TO_LONGS(ep->num_ib_windows),
-+ GFP_KERNEL);
-+ if (!ep->ib_window_map)
-+ return -ENOMEM;
-+
-+ ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
-+ BITS_TO_LONGS(ep->num_ob_windows),
-+ GFP_KERNEL);
-+ if (!ep->ob_window_map)
-+ return -ENOMEM;
-
- addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
- GFP_KERNEL);
-@@ -315,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
+@@ -333,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
return -ENOMEM;
ep->outbound_addr = addr;
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
if (ret < 0)
epc->max_functions = 1;
-@@ -335,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
+@@ -353,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
return ret;
}
/*
* Maximum number of MSI IRQs can be 256 per controller. But keep
* it 32 as of now. Probably we will never need more than 32. If needed,
-@@ -114,6 +102,10 @@
- #define MAX_MSI_IRQS 32
- #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
+@@ -118,6 +106,10 @@
+ #define MAX_IATU_IN 256
+ #define MAX_IATU_OUT 256
+/* Maximum number of inbound/outbound iATUs */
+#define MAX_IATU_IN 256
struct pcie_port;
struct dw_pcie;
struct dw_pcie_ep;
-@@ -181,8 +173,8 @@ enum dw_pcie_as_type {
+@@ -185,8 +177,8 @@ enum dw_pcie_as_type {
struct dw_pcie_ep_ops {
void (*ep_init)(struct dw_pcie_ep *ep);
};
struct dw_pcie_ep {
-@@ -193,10 +185,14 @@ struct dw_pcie_ep {
- size_t page_size;
- u8 bar_to_atu[6];
- phys_addr_t *outbound_addr;
-- unsigned long ib_window_map;
-- unsigned long ob_window_map;
-+ unsigned long *ib_window_map;
-+ unsigned long *ob_window_map;
+@@ -201,6 +193,10 @@ struct dw_pcie_ep {
+ unsigned long *ob_window_map;
u32 num_ib_windows;
u32 num_ob_windows;
-+ void __iomem *msi_mem;
-+ phys_addr_t msi_mem_phys;
-+ u8 msi_cap; /* MSI capability offset */
-+ u8 msix_cap; /* MSI-X capability offset */
++ void __iomem *msi_mem;
++ phys_addr_t msi_mem_phys;
++ u8 msi_cap; /* MSI capability offset */
++ u8 msix_cap; /* MSI-X capability offset */
};
struct dw_pcie_ops {
-@@ -335,6 +331,12 @@ static inline int dw_pcie_host_init(stru
+@@ -339,6 +335,12 @@ static inline int dw_pcie_host_init(stru
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
#else
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
{
-@@ -348,5 +350,26 @@ static inline int dw_pcie_ep_init(struct
+@@ -352,5 +354,26 @@ static inline int dw_pcie_ep_init(struct
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
}
#endif /* __UAPI_LINUX_PCITEST_H */
--- a/tools/pci/pcitest.c
+++ b/tools/pci/pcitest.c
-@@ -31,12 +31,17 @@
+@@ -30,12 +30,17 @@
#define BILLION 1E9
static char *result[] = { "NOT OKAY", "OKAY" };
bool read;
bool write;
bool copy;
-@@ -65,6 +70,24 @@ static int run_test(struct pci_test *tes
+@@ -62,6 +67,24 @@ static int run_test(struct pci_test *tes
fprintf(stdout, "%s\n", result[ret]);
}
if (test->legacyirq) {
ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
fprintf(stdout, "LEGACY IRQ:\t");
-@@ -83,6 +106,15 @@ static int run_test(struct pci_test *tes
+@@ -80,6 +103,15 @@ static int run_test(struct pci_test *tes
fprintf(stdout, "%s\n", result[ret]);
}
if (test->write) {
ret = ioctl(fd, PCITEST_WRITE, test->size);
fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
-@@ -133,7 +165,7 @@ int main(int argc, char **argv)
+@@ -130,7 +162,7 @@ int main(int argc, char **argv)
/* set default endpoint device */
test->device = "/dev/pci-endpoint-test.0";
switch (c) {
case 'D':
test->device = optarg;
-@@ -151,6 +183,20 @@ int main(int argc, char **argv)
+@@ -148,6 +180,20 @@ int main(int argc, char **argv)
if (test->msinum < 1 || test->msinum > 32)
goto usage;
continue;
case 'r':
test->read = true;
continue;
-@@ -173,6 +219,9 @@ usage:
+@@ -170,6 +216,9 @@ usage:
"\t-D <dev> PCI endpoint test device {default: /dev/pci-endpoint-test.0}\n"
"\t-b <bar num> BAR test (bar number between 0..5)\n"
"\t-m <msi num> MSI test (msi number between 1..32)\n"
projects / openwrt / openwrt.git / blobdiff