-From 2b2e3b9a0d2abf276b40843f75d97b623e4ee109 Mon Sep 17 00:00:00 2001
+From 1806d342beb334c8cb0a438315ad5529262b2791 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Mon, 25 Sep 2017 10:02:10 +0800
-Subject: [PATCH] dts: support layercape
+Date: Wed, 17 Jan 2018 14:52:50 +0800
+Subject: [PATCH 04/30] dts: support layercape
-This is a integrated patch for layerscape dts support.
+This is an integrated patch for layerscape dts support.
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/imx6ul.dtsi | 4 +-
arch/arm/boot/dts/keystone.dtsi | 4 +-
- arch/arm/boot/dts/ls1021a-qds.dts | 13 +
- arch/arm/boot/dts/ls1021a-twr.dts | 13 +
- arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
+ arch/arm/boot/dts/ls1021a-qds.dts | 21 +
+ arch/arm/boot/dts/ls1021a-twr.dts | 25 +
+ arch/arm/boot/dts/ls1021a.dtsi | 197 +++--
arch/arm/boot/dts/mt6580.dtsi | 2 +-
arch/arm/boot/dts/mt6589.dtsi | 2 +-
arch/arm/boot/dts/mt8127.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
- arch/arm64/boot/dts/freescale/Makefile | 16 +
- arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 134 +++
- arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 155 ++++
- arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 91 +++
- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 517 ++++++++++++
+ arch/arm64/boot/dts/freescale/Makefile | 17 +
+ .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 202 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 138 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 602 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
.../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
.../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
.../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 308 ++++++-
arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
- .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
+ .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 110 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
- .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
+ .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 83 ++
.../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 800 ++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 816 ++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 825 ++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 910 +++++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 919 +++++++++++++++++++++
.../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
- arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
+ arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 73 ++
.../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
.../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
.../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
- 66 files changed, 7778 insertions(+), 1021 deletions(-)
+ 67 files changed, 8231 insertions(+), 1022 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy1c>;
+@@ -331,3 +344,11 @@
+ &uart1 {
+ status = "okay";
+ };
++
++&can0 {
++ status = "okay";
++};
++
++&can1 {
++ status = "okay";
++};
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -142,6 +142,19 @@
&enet0 {
tbi-handle = <&tbi1>;
phy-handle = <&sgmii_phy2>;
+@@ -228,6 +241,10 @@
+ };
+ };
+
++&esdhc {
++ status = "okay";
++};
++
+ &sai1 {
+ status = "okay";
+ };
+@@ -243,3 +260,11 @@
+ &uart1 {
+ status = "okay";
+ };
++
++&can0 {
++ status = "okay";
++};
++
++&can1 {
++ status = "okay";
++};
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -74,17 +74,24 @@
};
+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ftm-alarm";
++ compatible = "fsl,ls1021a-ftm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+
+ qdma: qdma@8390000 {
+ compatible = "fsl,ls1021a-qdma";
-+ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
-+ <0x0 0x8389000 0x0 0x1000>, /* Status regs */
-+ <0x0 0x838a000 0x0 0x2000>; /* Block regs */
++ reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */
++ <0x0 0x8399000 0x0 0x1000>, /* Status regs */
++ <0x0 0x839a000 0x0 0x2000>; /* Block regs */
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "qdma-error", "qdma-queue";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+@@ -674,5 +697,45 @@
+ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ };
++
++ can0: can@2a70000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2a70000 0x0 0x1000>;
++ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
++
++ can1: can@2a80000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2a80000 0x0 0x1000>;
++ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
++
++ can2: can@2a90000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2a90000 0x0 0x1000>;
++ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
++
++ can3: can@2aa0000 {
++ compatible = "fsl,ls1021ar2-flexcan";
++ reg = <0x0 0x2aa0000 0x0 0x1000>;
++ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++ clock-names = "ipg", "per";
++ big-endian;
++ status = "disabled";
++ };
+ };
+ };
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -91,7 +91,7 @@
};
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -1109,7 +1109,7 @@
+@@ -1110,7 +1110,7 @@
#address-cells = <0>;
reg = <0xffc01000 0x1000>,
interrupt-controller;
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -1,8 +1,24 @@
+@@ -1,8 +1,25 @@
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+@@ -0,0 +1,123 @@
++/*
++ * Device Tree file for NXP LS1012A 2G5RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++ model = "LS1012A 2G5RDB Board";
++ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++};
++
++&duart0 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++};
++
++&qspi {
++ num-cs = <2>;
++ bus-num = <0>;
++ status = "okay";
++
++ qflash0: s25fs512s@0 {
++ compatible = "spansion,m25p80";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-max-frequency = <20000000>;
++ m25p,fast-read;
++ reg = <0>;
++ };
++};
++
++&sata {
++ status = "okay";
++};
++
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
+--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-@@ -0,0 +1,134 @@
+@@ -0,0 +1,177 @@
+/*
+ * Device Tree file for Freescale LS1012A Freedom Board.
+ *
+ model = "LS1012A Freedom Board";
+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
+
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
++
+&sai2 {
+ status = "okay";
+};
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-@@ -0,0 +1,155 @@
+@@ -0,0 +1,202 @@
+/*
+ * Device Tree file for Freescale LS1012A QDS Board.
+ *
+ model = "LS1012A QDS Board";
+ compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
+
++&pcie {
++ status = "okay";
++};
++
+&duart0 {
+ status = "okay";
+};
+ };
+};
+
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x2>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x3>;
++ phy-mode = "sgmii-2500";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
++
+&sai2 {
+ status = "okay";
+};
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-@@ -0,0 +1,91 @@
+@@ -0,0 +1,138 @@
+/*
+ * Device Tree file for Freescale LS1012A RDB Board.
+ *
+/ {
+ model = "LS1012A RDB Board";
+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++};
++
++&pcie {
++ status = "okay";
+};
+
+&duart0 {
+ mmc-hs200-1_8v;
+ status = "okay";
+};
++
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x1>; /* enabled/disabled */
++ };
++ };
++
++ ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
++ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "rgmii-txid";
++ fsl,pfe-phy-if-flags = <0x0>;
++
++ mdio@0 {
++ reg = <0x0>; /* enabled/disabled */
++ };
++ };
++};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -0,0 +1,517 @@
+@@ -0,0 +1,602 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ caam-dma {
++ compatible = "fsl,sec-v5.4-dma",
++ "fsl,sec-v5.0-dma",
++ "fsl,sec-v4.0-dma";
++ };
++
+ rtic@60000 {
+ compatible = "fsl,sec-v5.4-rtic",
+ "fsl,sec-v5.0-rtic",
+ status = "disabled";
+ };
+
++ rcpm: rcpm@1ee2000 {
++ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
++ reg = <0x0 0x1ee2000 0x0 0x1000>;
++ fsl,#rcpm-wakeup-cells = <1>;
++ };
++
+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ftm-alarm";
++ compatible = "fsl,ls1012a-ftm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 0>;
++ clocks = <&clockgen 4 3>;
+ status = "disabled";
+ };
+
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 0>;
++ clocks = <&clockgen 4 3>;
+ status = "disabled";
+ };
+
+ dma-coherent;
+ status = "disabled";
+ };
++
++ msi: msi-controller1@1572000 {
++ compatible = "fsl,ls1012a-msi";
++ reg = <0x0 0x1572000 0x0 0x8>;
++ msi-controller;
++ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ pcie: pcie@3400000 {
++ compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
++ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
++ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++ reg-names = "regs", "config";
++ interrupts = <0 118 0x4>, /* AER interrupt */
++ <0 117 0x4>; /* PME interrupt */
++ interrupt-names = "aer", "pme";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ num-lanes = <4>;
++ bus-range = <0x0 0xff>;
++ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
++ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++ msi-parent = <&msi>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
++ <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++ };
++
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ pfe_reserved: packetbuffer@83400000 {
++ reg = <0 0x83400000 0 0xc00000>;
++ };
++ };
++
++ pfe: pfe@04000000 {
++ compatible = "fsl,pfe";
++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
++ reg-names = "pfe", "pfe-ddr";
++ fsl,pfe-num-interfaces = <0x2>;
++ interrupts = <0 172 0x4>, /* HIF interrupt */
++ <0 173 0x4>, /*HIF_NOCPY interrupt */
++ <0 174 0x4>; /* WoL interrupt */
++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++ memory-region = <&pfe_reserved>;
++ fsl,pfe-scfg = <&scfg 0>;
++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++ clocks = <&clockgen 4 0>;
++ clock-names = "pfe";
++
++ status = "okay";
++ pfe_mac0: ethernet@0 {
++ };
++
++ pfe_mac1: ethernet@1 {
++ };
++ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
+ };
+};
--- /dev/null
};
+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ftm-alarm";
++ compatible = "fsl,ls1043a-ftm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
-@@ -608,3 +869,6 @@
+@@ -607,4 +868,13 @@
+ };
};
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
};
+
+#include "qoriq-qman1-portals.dtsi"
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
-@@ -0,0 +1,109 @@
+@@ -0,0 +1,110 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet7>;
++ dma-coherent;
+ };
+};
+
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
-@@ -0,0 +1,76 @@
+@@ -0,0 +1,83 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+};
+
+&fsldpaa {
++ ethernet@0 {
++ status = "disabled";
++ };
++ ethernet@1 {
++ status = "disabled";
++ };
+ ethernet@9 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet7>;
++ dma-coherent;
+ };
+};
+
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -0,0 +1,793 @@
+@@ -0,0 +1,800 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ };
+
+ ftm0: ftm0@29d0000 {
-+ compatible = "fsl,ftm-alarm";
++ compatible = "fsl,ls1046a-ftm";
+ reg = <0x0 0x29d0000 0x0 0x10000>,
+ <0x0 0x1ee2140 0x0 0x4>;
+ reg-names = "ftm", "FlexTimer1";
+ no-map;
+ };
+ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
+};
+
+#include "qoriq-qman1-portals.dtsi"
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-@@ -0,0 +1,816 @@
+@@ -0,0 +1,825 @@
+/*
+ * Device Tree Include file for NXP Layerscape-1088A family SoC.
+ *
+ };
+
+ ftm0: ftm0@2800000 {
-+ compatible = "fsl,ftm-alarm";
-+ reg = <0x0 0x2800000 0x0 0x10000>;
++ compatible = "fsl,ls1088a-ftm";
++ reg = <0x0 0x2800000 0x0 0x10000>,
++ <0x0 0x1e34050 0x0 0x4>;
+ interrupts = <0 44 4>;
++ reg-names = "ftm", "FlexTimer1";
+ };
+
+ i2c0: i2c@2000000 {
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ };
+ };
+
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
++
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-@@ -0,0 +1,910 @@
+@@ -0,0 +1,919 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-2080A family SoC.
+ *
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ clock-names = "i2c";
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ i2c1: i2c@2010000 {
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ clock-names = "i2c";
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ i2c2: i2c@2020000 {
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ clock-names = "i2c";
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ i2c3: i2c@2030000 {
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ clock-names = "i2c";
-+ clocks = <&clockgen 4 3>;
++ clocks = <&clockgen 4 1>;
+ };
+
+ ifc: ifc@2240000 {
+ };
+
+ ftm0: ftm0@2800000 {
-+ compatible = "fsl,ftm-alarm";
-+ reg = <0x0 0x2800000 0x0 0x10000>;
++ compatible = "fsl,ls208xa-ftm";
++ reg = <0x0 0x2800000 0x0 0x10000>,
++ <0x0 0x1e34050 0x0 0x4>;
+ interrupts = <0 44 4>;
++ reg-names = "ftm", "FlexTimer1";
+ };
+ };
+
+ interrupts = <0 18 0x4>;
+ little-endian;
+ };
++
++ firmware {
++ optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
-@@ -0,0 +1,66 @@
+@@ -0,0 +1,73 @@
+/*
+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
+ *
+ ethernet@0 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet0>;
++ dma-coherent;
+ };
+ ethernet@1 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet1>;
++ dma-coherent;
+ };
+ ethernet@2 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet2>;
++ dma-coherent;
+ };
+ ethernet@3 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet3>;
++ dma-coherent;
+ };
+ ethernet@4 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet4>;
++ dma-coherent;
+ };
+ ethernet@5 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet5>;
++ dma-coherent;
+ };
+ ethernet@8 {
+ compatible = "fsl,dpa-ethernet";
+ fsl,fman-mac = <&enet6>;
++ dma-coherent;
+ };
+};
+
projects / openwrt / openwrt.git / blobdiff