mediatek: don't break auxadc without 32k clk

[openwrt/openwrt.git] / target / linux / mediatek / patches-5.15 / 501-auxadc-add-auxadc-32k-clk.patch

diff --git a/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch
index a49fbca4ee70f7d5f8e9b50539f951deb630293c..5b98235ff413b00a2f9d68c29158a6e29a85d34c 100644 (file)
--- a/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch
+++ b/target/linux/mediatek/patches-5.15/501-auxadc-add-auxadc-32k-clk.patch
@@ -8,14 +8,16 @@
        struct mutex lock;
        const struct mtk_auxadc_compatible *dev_comp;
  };
-@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_
+@@ -222,6 +223,14 @@ static int __maybe_unused mt6577_auxadc_
                return ret;
        }
  
-+      ret = clk_prepare_enable(adc_dev->adc_32k_clk);
-+      if (ret) {
-+              pr_err("failed to enable auxadc clock\n");
-+              return ret;
++      if (!IS_ERR(adc_dev->adc_32k_clk)) {
++              ret = clk_prepare_enable(adc_dev->adc_32k_clk);
++              if (ret) {
++                      pr_err("failed to enable auxadc clock\n");
++                      return ret;
++              }
 +      }
 +
        mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,