/dts-v1/;
-/include/ "mt7620a.dtsi"
+#include "mt7620a.dtsi"
/ {
compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
model = "Ralink MT7620a + MT7530 evaluation board";
+};
+
+&spi0 {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
- palmbus@10000000 {
- spi@b00 {
- status = "okay";
-
- m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25fl064k";
- reg = <0 0>;
- linux,modalias = "m25p80", "s25fl064k";
- spi-max-frequency = <10000000>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x30000>;
- read-only;
- };
-
- partition@30000 {
- label = "u-boot-env";
- reg = <0x30000 0x10000>;
- read-only;
- };
-
- factory: partition@40000 {
- label = "factory";
- reg = <0x40000 0x10000>;
- read-only;
- };
-
- partition@50000 {
- label = "firmware";
- reg = <0x50000 0x7b0000>;
- };
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ partition@50000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x50000 0x7b0000>;
};
};
};
+};
- pinctrl {
- state_default: pinctrl0 {
- gpio {
- ralink,group = "i2c", "uartf";
- ralink,function = "gpio";
- };
+&pinctrl {
+ state_default: pinctrl0 {
+ gpio {
+ ralink,group = "i2c", "uartf";
+ ralink,function = "gpio";
};
};
+};
+
+ðernet {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
+ mediatek,portmap = "llllw";
+
+ port@5 {
+ status = "okay";
+ mediatek,fixed-link = <1000 1 1 1>;
+ phy-mode = "rgmii";
+ };
- ethernet@10100000 {
+ mdio-bus {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
- ralink,port-map = "llllw";
- port@5 {
- status = "okay";
- ralink,fixed-link = <1000 1 1 1>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
phy-mode = "rgmii";
};
- mdio-bus {
- status = "okay";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- phy-mode = "rgmii";
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- phy-mode = "rgmii";
- };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ phy-mode = "rgmii";
+ };
- phy2: ethernet-phy@2 {
- reg = <2>;
- phy-mode = "rgmii";
- };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ phy-mode = "rgmii";
+ };
- phy3: ethernet-phy@3 {
- reg = <3>;
- phy-mode = "rgmii";
- };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ phy-mode = "rgmii";
+ };
- phy4: ethernet-phy@4 {
- reg = <4>;
- phy-mode = "rgmii";
- };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ phy-mode = "rgmii";
+ };
- phy1f: ethernet-phy@1f {
- reg = <0x1f>;
- phy-mode = "rgmii";
- };
+ phy1f: ethernet-phy@1f {
+ reg = <0x1f>;
+ phy-mode = "rgmii";
};
};
+};
- gsw@10110000 {
- ralink,port4 = "gmac";
- mediatek,mt7530 = <1>;
- };
+&gsw {
+ mediatek,port4 = "gmac";
+};
- pcie@10140000 {
- status = "okay";
- };
+&pcie {
+ status = "okay";
+};
- ehci@101c0000 {
- status = "okay";
- };
+&ehci {
+ status = "okay";
+};
- ohci@101c1000 {
- status = "okay";
- };
+&ohci {
+ status = "okay";
};