/ {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "mediatek,mtk7621-soc";
+ compatible = "mediatek,mt7621-soc";
cpus {
cpu@0 {
};
};
+ i2c: i2c@900 {
+ compatible = "mediatek,mt7621-i2c";
+ reg = <0x900 0x100>;
+
+ clocks = <&sysclock>;
+
+ resets = <&rstctrl 16>;
+ reset-names = "i2c";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ };
+
+ i2s: i2s@a00 {
+ compatible = "mediatek,mt7621-i2s";
+ reg = <0xa00 0x100>;
+
+ clocks = <&sysclock>;
+
+ resets = <&rstctrl 17>;
+ reset-names = "i2s";
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
+
+ txdma-req = <2>;
+ rxdma-req = <3>;
+
+ dmas = <&gdma 4>,
+ <&gdma 6>;
+ dma-names = "tx", "rx";
+
+ status = "disabled";
+ };
+
memc: memc@5000 {
compatible = "mtk,mt7621-memc";
reg = <0x300 0x100>;
};
spi0: spi@b00 {
- status = "okay";
+ status = "disabled";
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
-
- m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <10000000>;
- m25p,chunked-io = <32>;
- };
};
gdma: gdma@2800 {
state_default: pinctrl0 {
};
- spi_pins: spi {
- spi {
- ralink,group = "spi";
- ralink,function = "spi";
- };
- };
-
i2c_pins: i2c {
i2c {
ralink,group = "i2c";
};
};
+ spi_pins: spi {
+ spi {
+ ralink,group = "spi";
+ ralink,function = "spi";
+ };
+ };
+
uart1_pins: uart1 {
uart1 {
ralink,group = "uart1";
};
sdhci: sdhci@1E130000 {
+ status = "disabled";
+
compatible = "ralink,mt7620-sdhci";
reg = <0x1E130000 0x4000>;
GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
+ status = "disabled";
resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
reset-names = "pcie0", "pcie1", "pcie2";