ramips: fix MT7621 dtsi

[openwrt/openwrt.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index cb830128d8f029c20b2638a763f4cede8aaa2d9b..77841a61d297cf2ccb32429d6bc6d4f7994bce86 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/clock/mt7621-clk.h>
 
 / {
        #address-cells = <1>;
@@ -33,12 +34,11 @@
                serial0 = &uartlite;
        };
 
-       cpuclock: cpuclock {
-               #clock-cells = <0>;
-               compatible = "fixed-clock";
+       pll: pll {
+               compatible = "mediatek,mt7621-pll", "syscon";
 
-               /* FIXME: there should be way to detect this */
-               clock-frequency = <880000000>;
+               #clock-cells = <1>;
+               clock-output-names = "cpu", "bus";
        };
 
        sysclock: sysclock {
@@ -138,9 +138,9 @@
                        status = "disabled";
                };
 
-               systick: systick@d00 {
+               systick: systick@500 {
                        compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
-                       reg = <0xd00 0x10>;
+                       reg = <0x500 0x10>;
 
                        resets = <&rstctrl 28>;
                        reset-names = "intc";
@@ -151,24 +151,23 @@
 
                memc: memc@5000 {
                        compatible = "mtk,mt7621-memc";
-                       reg = <0x300 0x100>;
+                       reg = <0x5000 0x1000>;
                };
 
                cpc: cpc@1fbf0000 {
-                            compatible = "mtk,mt7621-cpc";
-                            reg = <0x1fbf0000 0x8000>;
+                       compatible = "mtk,mt7621-cpc";
+                       reg = <0x1fbf0000 0x8000>;
                };
 
                mc: mc@1fbf8000 {
-                           compatible = "mtk,mt7621-mc";
-                           reg = <0x1fbf8000 0x8000>;
-               };
+                       compatible = "mtk,mt7621-mc";
+                       reg = <0x1fbf8000 0x8000>;
+               };
 
                uartlite: uartlite@c00 {
                        compatible = "ns16550a";
                        reg = <0xc00 0x100>;
 
-                       clocks = <&sysclock>;
                        clock-frequency = <50000000>;
 
                        interrupt-parent = <&gic>;
@@ -179,13 +178,49 @@
                        no-loopback-test;
                };
 
+               uartlite2: uartlite2@d00 {
+                       compatible = "ns16550a";
+                       reg = <0xd00 0x100>;
+
+                       clock-frequency = <50000000>;
+
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
+
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_pins>;
+
+                       status = "disabled";
+               };
+
+               uartlite3: uartlite3@e00 {
+                       compatible = "ns16550a";
+                       reg = <0xe00 0x100>;
+
+                       clock-frequency = <50000000>;
+
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
+
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart3_pins>;
+
+                       status = "disabled";
+               };
+
                spi0: spi@b00 {
                        status = "disabled";
 
                        compatible = "ralink,mt7621-spi";
                        reg = <0xb00 0x100>;
 
-                       clocks = <&sysclock>;
+                       clocks = <&pll MT7621_CLK_BUS>;
 
                        resets = <&rstctrl 18>;
                        reset-names = "spi";
@@ -240,15 +275,15 @@
                state_default: pinctrl0 {
                };
 
-               i2c_pins: i2c {
-                       i2c {
+               i2c_pins: i2c_pins {
+                       i2c_pins {
                                ralink,group = "i2c";
                                ralink,function = "i2c";
                        };
                };
 
-               spi_pins: spi {
-                       spi {
+               spi_pins: spi_pins {
+                       spi_pins {
                                ralink,group = "spi";
                                ralink,function = "spi";
                        };
@@ -341,9 +376,14 @@
 
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdhci_pins>;
        };
 
        xhci: xhci@1E1C0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
                status = "okay";
 
                compatible = "mediatek,mt8173-xhci";
@@ -356,6 +396,25 @@
 
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
+
+               /*
+                * Port 1 of both hubs is one usb slot and referenced here.
+                * The binding doesn't allow to address individual hubs.
+                * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
+                */
+               xhci_ehci_port1: port@1 {
+                       reg = <1>;
+                       #trigger-source-cells = <0>;
+               };
+
+               /*
+                * Only the second usb hub has a second port. That port serves
+                * ehci and ohci.
+                */
+               ehci_port2: port@2 {
+                       reg = <2>;
+                       #trigger-source-cells = <0>;
+               };
        };
 
        gic: interrupt-controller@1fbc0000 {
@@ -370,7 +429,7 @@
                timer {
                        compatible = "mti,gic-timer";
                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-                       clocks = <&cpuclock>;
+                       clocks = <&pll MT7621_CLK_CPU>;
                };
        };
 
@@ -381,18 +440,6 @@
                bank-width = <2>;
                reg = <0x1e003000 0x800
                        0x1e003800 0x800>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-       };
-
-       hnat: hnat@1e100000 {
-               compatible = "mediatek,mt7623-hnat";
-               reg = <0x1e100000 0x10000>;
-               mtketh-ppd = "eth0";
-               mtketh-lan = "eth0";
-               mtketh-wan = "eth0";
-               resets = <&rstctrl 0>;
-               reset-names = "mtketh";
        };
 
        ethernet: ethernet@1e100000 {
@@ -400,7 +447,7 @@
                reg = <0x1e100000 0x10000>;
 
                #address-cells = <1>;
-               #size-cells = <0>;
+               #size-cells = <1>;
 
                resets = <&rstctrl 6 &rstctrl 23>;
                reset-names = "fe", "eth";
@@ -419,6 +466,16 @@
                                phy-mode = "rgmii";
                        };
                };
+
+               hnat: hnat@0 {
+                       compatible = "mediatek,mt7623-hnat";
+                       reg = <0 0x10000>;
+                       mtketh-ppd = "eth0";
+                       mtketh-lan = "eth0";
+                       mtketh-wan = "eth0";
+                       resets = <&rstctrl 0>;
+                       reset-names = "mtketh";
+               };
        };
 
        gsw: gsw@1e110000 {
@@ -459,25 +516,31 @@
                clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
                clock-names = "pcie0", "pcie1", "pcie2";
 
-               pcie0 {
+               pcie0: pcie@0,0 {
                        reg = <0x0000 0 0 0 0>;
 
                        #address-cells = <3>;
                        #size-cells = <2>;
+
+                       ranges;
                };
 
-               pcie1 {
+               pcie1: pcie@1,0 {
                        reg = <0x0800 0 0 0 0>;
 
                        #address-cells = <3>;
                        #size-cells = <2>;
+
+                       ranges;
                };
 
-               pcie2 {
+               pcie2: pcie@2,0 {
                        reg = <0x1000 0 0 0 0>;
 
                        #address-cells = <3>;
                        #size-cells = <2>;
+
+                       ranges;
                };
        };
 };