ramips: set usb led trigger via devicetree

[openwrt/openwrt.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index cb830128d8f029c20b2638a763f4cede8aaa2d9b..aa85aee6cb38935d9478fc395934b216a0781a5f 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -155,14 +155,14 @@
                };
 
                cpc: cpc@1fbf0000 {
-                            compatible = "mtk,mt7621-cpc";
-                            reg = <0x1fbf0000 0x8000>;
+                       compatible = "mtk,mt7621-cpc";
+                       reg = <0x1fbf0000 0x8000>;
                };
 
                mc: mc@1fbf8000 {
-                           compatible = "mtk,mt7621-mc";
-                           reg = <0x1fbf8000 0x8000>;
-               };
+                       compatible = "mtk,mt7621-mc";
+                       reg = <0x1fbf8000 0x8000>;
+               };
 
                uartlite: uartlite@c00 {
                        compatible = "ns16550a";
@@ -341,9 +341,14 @@
 
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdhci_pins>;
        };
 
        xhci: xhci@1E1C0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
                status = "okay";
 
                compatible = "mediatek,mt8173-xhci";
@@ -356,6 +361,25 @@
 
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
+
+               /*
+                * Port 1 of both hubs is one usb slot and referenced here.
+                * The binding doesn't allow to address individual hubs.
+                * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
+                */
+               xhci_ehci_port1: port@1 {
+                       reg = <1>;
+                       #trigger-source-cells = <0>;
+               };
+
+               /*
+                * Only the second usb hub has a second port. That port serves
+                * ehci and ohci.
+                */
+               ehci_port2: port@2 {
+                       reg = <2>;
+                       #trigger-source-cells = <0>;
+               };
        };
 
        gic: interrupt-controller@1fbc0000 {
@@ -381,18 +405,6 @@
                bank-width = <2>;
                reg = <0x1e003000 0x800
                        0x1e003800 0x800>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-       };
-
-       hnat: hnat@1e100000 {
-               compatible = "mediatek,mt7623-hnat";
-               reg = <0x1e100000 0x10000>;
-               mtketh-ppd = "eth0";
-               mtketh-lan = "eth0";
-               mtketh-wan = "eth0";
-               resets = <&rstctrl 0>;
-               reset-names = "mtketh";
        };
 
        ethernet: ethernet@1e100000 {
@@ -400,7 +412,7 @@
                reg = <0x1e100000 0x10000>;
 
                #address-cells = <1>;
-               #size-cells = <0>;
+               #size-cells = <1>;
 
                resets = <&rstctrl 6 &rstctrl 23>;
                reset-names = "fe", "eth";
@@ -419,6 +431,16 @@
                                phy-mode = "rgmii";
                        };
                };
+
+               hnat: hnat@0 {
+                       compatible = "mediatek,mt7623-hnat";
+                       reg = <0 0x10000>;
+                       mtketh-ppd = "eth0";
+                       mtketh-lan = "eth0";
+                       mtketh-wan = "eth0";
+                       resets = <&rstctrl 0>;
+                       reset-names = "mtketh";
+               };
        };
 
        gsw: gsw@1e110000 {
@@ -459,25 +481,31 @@
                clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
                clock-names = "pcie0", "pcie1", "pcie2";
 
-               pcie0 {
+               pcie0: pcie@0,0 {
                        reg = <0x0000 0 0 0 0>;
 
                        #address-cells = <3>;
                        #size-cells = <2>;
+
+                       ranges;
                };
 
-               pcie1 {
+               pcie1: pcie@1,0 {
                        reg = <0x0800 0 0 0 0>;
 
                        #address-cells = <3>;
                        #size-cells = <2>;
+
+                       ranges;
                };
 
-               pcie2 {
+               pcie2: pcie@2,0 {
                        reg = <0x1000 0 0 0 0>;
 
                        #address-cells = <3>;
                        #size-cells = <2>;
+
+                       ranges;
                };
        };
 };