ramips: update dtsi files to support second spi device

[openwrt/openwrt.git] / target / linux / ramips / dts / rt3352.dtsi

diff --git a/target/linux/ramips/dts/rt3352.dtsi b/target/linux/ramips/dts/rt3352.dtsi
index b04845c4c905a11cab94f5067de3e93703c1800c..ffb9336f6c95a6ebed6e9386a9db968bfde8201b 100644 (file)
--- a/target/linux/ramips/dts/rt3352.dtsi
+++ b/target/linux/ramips/dts/rt3352.dtsi
@@ -20,6 +20,11 @@
                compatible = "mti,cpu-interrupt-controller";
        };
 
+       aliases {
+               spi0 = &spi0;
+               spi1 = &spi1;
+       };
+
        palmbus@10000000 {
                compatible = "palmbus";
                reg = <0x10000000 0x200000>;
@@ -140,9 +145,9 @@
                        status = "disabled";
                };
 
-               spi@b00 {
+               spi0: spi@b00 {
                        compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
-                       reg = <0xb00 0x100>;
+                       reg = <0xb00 0x40>;
                        #address-cells = <1>;
                        #size-cells = <0>;
 
@@ -155,6 +160,21 @@
                        status = "disabled";
                };
 
+               spi1: spi@b40 {
+                       compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
+                       reg = <0xb40 0x60>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi_cs1>;
+
+                       status = "disabled";
+               };
+
                uartlite@c00 {
                        compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
@@ -188,6 +208,13 @@
                        };
                };
 
+               spi_cs1: spi1 {
+                       spi1 {
+                               ralink,group = "spi_cs1";
+                               ralink,function = "spi_cs1";
+                       };
+               };
+
                uartlite_pins: uartlite {
                        uart {
                                ralink,group = "uartlite";