ramips: update dtsi files to support second spi device
[openwrt/openwrt.git] / target / linux / ramips / dts / rt3883.dtsi
index dc267824b91360f49871cd7cad70b4b5b82dd256..6592b3bacfcf5911fa9e5d096bed7135eac902c8 100644 (file)
@@ -15,6 +15,7 @@
 
        aliases {
                spi0 = &spi0;
 
        aliases {
                spi0 = &spi0;
+               spi1 = &spi1;
        };
 
        cpuintc: cpuintc@0 {
        };
 
        cpuintc: cpuintc@0 {
 
                spi0: spi@b00 {
                        compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
 
                spi0: spi@b00 {
                        compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
-                       reg = <0xb00 0x100>;
+                       reg = <0xb00 0x40>;
                        #address-cells = <1>;
                        #size-cells = <0>;
 
                        #address-cells = <1>;
                        #size-cells = <0>;
 
                        status = "disabled";
                };
 
                        status = "disabled";
                };
 
+               spi1: spi@b40 {
+                       compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
+                       reg = <0xb40 0x60>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       resets = <&rstctrl 18>;
+                       reset-names = "spi";
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi_cs1>;
+
+                       status = "disabled";
+               };
+
                uartlite@c00 {
                        compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
                uartlite@c00 {
                        compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
                        reg = <0xc00 0x100>;
                        };
                };
 
                        };
                };
 
+               spi_cs1: spi1 {
+                       spi1 {
+                               ralink,group = "spi_cs1";
+                               ralink,function = "spi_cs1";
+                       };
+               };
+
                uartlite_pins: uartlite {
                        uart {
                                ralink,group = "uartlite";
                uartlite_pins: uartlite {
                        uart {
                                ralink,group = "uartlite";