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ramips: mt7620: enable all ports unconditionally
[openwrt/openwrt.git]
/
target
/
linux
/
ramips
/
files-4.14
/
drivers
/
net
/
ethernet
/
mediatek
/
gsw_mt7620.c
diff --git
a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
index b1f1794bc98bb2ed27bd8e13b03fa3cbabad2345..ecd056e27b564497606e2cf20eba92e5674a474c 100644
(file)
--- a/
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
+++ b/
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c
@@
-83,6
+83,8
@@
static int mt7620_mdio_mode(struct device_node *eth_node)
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
{
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
{
+ u32 i;
+ u32 val;
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
@@
-151,6
+153,14
@@
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
/* global page 1 */
_mt7620_mii_write(gsw, 1, 31, 0x1000);
_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
/* global page 1 */
_mt7620_mii_write(gsw, 1, 31, 0x1000);
_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
+
+ /* turn on all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, i, 0);
+ val &= ~BIT(11);
+ _mt7620_mii_write(gsw, i, 0, val);
+ }
+
}
/* global page 0 */
}
/* global page 0 */
@@
-187,7
+197,6
@@
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
_mt7620_mii_write(gsw, 4, 30, 0xa000);
_mt7620_mii_write(gsw, 4, 4, 0x05e1);
_mt7620_mii_write(gsw, 4, 16, 0x1313);
_mt7620_mii_write(gsw, 4, 30, 0xa000);
_mt7620_mii_write(gsw, 4, 4, 0x05e1);
_mt7620_mii_write(gsw, 4, 16, 0x1313);
- _mt7620_mii_write(gsw, 4, 0, 0x3100);
pr_info("gsw: setting port4 to ephy mode\n");
} else if (!mdio_mode) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
pr_info("gsw: setting port4 to ephy mode\n");
} else if (!mdio_mode) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);