upgrade 3.13 targets to 3.13.2, refresh patches

[openwrt/openwrt.git] / target / linux / sunxi / patches-3.13 / 118-clk-sunxi-add-pll5-pll6.patch

diff --git a/target/linux/sunxi/patches-3.13/118-clk-sunxi-add-pll5-pll6.patch b/target/linux/sunxi/patches-3.13/118-clk-sunxi-add-pll5-pll6.patch
index 425c92955eae94a45a90617e8d3a02f99ea0f9b4..6cff37f78cbe7b53ba072603bab05c044b4cdf10 100644 (file)
--- a/target/linux/sunxi/patches-3.13/118-clk-sunxi-add-pll5-pll6.patch
+++ b/target/linux/sunxi/patches-3.13/118-clk-sunxi-add-pll5-pll6.patch
@@ -16,8 +16,6 @@ Acked-by: Mike Turquette <mturquette@linaro.org>
  drivers/clk/sunxi/clk-sunxi.c                     | 230 ++++++++++++++++++++++
  2 files changed, 232 insertions(+)
 
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index b8c6cc4..80b2a39 100644
 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
 @@ -9,6 +9,8 @@ Required properties:
@@ -29,11 +27,9 @@ index b8c6cc4..80b2a39 100644
        "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
        "allwinner,sun4i-axi-clk" - for the AXI clock
        "allwinner,sun4i-axi-gates-clk" - for the AXI gates
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 96ccb3c..649d7c3 100644
 --- a/drivers/clk/sunxi/clk-sunxi.c
 +++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -218,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
+@@ -218,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u
  }
  
  /**
@@ -74,7 +70,7 @@ index 96ccb3c..649d7c3 100644
   * sun4i_get_apb1_factors() - calculates m, p factors for APB1
   * APB1 rate is calculated as follows
   * rate = (parent_rate >> p) / (m + 1);
-@@ -293,6 +327,13 @@ struct factors_data {
+@@ -293,6 +327,13 @@ static struct clk_factors_config sun6i_a
        .mwidth = 2,
  };
  
@@ -88,7 +84,7 @@ index 96ccb3c..649d7c3 100644
  static struct clk_factors_config sun4i_apb1_config = {
        .mshift = 0,
        .mwidth = 5,
-@@ -312,6 +353,12 @@ struct factors_data {
+@@ -312,6 +353,12 @@ static const struct factors_data sun6i_a
        .getter = sun6i_a31_get_pll1_factors,
  };
  
@@ -101,7 +97,7 @@ index 96ccb3c..649d7c3 100644
  static const struct factors_data sun4i_apb1_data __initconst = {
        .table = &sun4i_apb1_config,
        .getter = sun4i_get_apb1_factors,
-@@ -627,6 +674,179 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
+@@ -627,6 +674,179 @@ static void __init sunxi_gates_clk_setup
        of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  }
  
@@ -281,7 +277,7 @@ index 96ccb3c..649d7c3 100644
  /* Matches for factors clocks */
  static const struct of_device_id clk_factors_match[] __initconst = {
        {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
-@@ -644,6 +864,13 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
+@@ -644,6 +864,13 @@ static const struct of_device_id clk_div
        {}
  };
  
@@ -295,7 +291,7 @@ index 96ccb3c..649d7c3 100644
  /* Matches for mux clocks */
  static const struct of_device_id clk_mux_match[] __initconst = {
        {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
-@@ -721,6 +948,9 @@ static void __init sunxi_init_clocks(struct device_node *np)
+@@ -721,6 +948,9 @@ static void __init sunxi_init_clocks(str
        /* Register divider clocks */
        of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
  
@@ -305,6 +301,3 @@ index 96ccb3c..649d7c3 100644
        /* Register mux clocks */
        of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
  
--- 
-1.8.5.1
-