Set -march=mips32

[openwrt/openwrt.git] / target / linux / xburst / files-2.6.32 / arch / mips / jz4740 / time.c

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
index b811fcd446375a0423668e476129c38e5c0990e0..77fc2012ed211dffcfef70da13771f452bf03985 100644 (file)
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
@@ -22,6 +22,7 @@
 #include <asm/mach-jz4740/irq.h>
 #include <asm/mach-jz4740/jz4740.h>
 #include <asm/time.h>
+#include "clock.h"
 
 #define JZ_REG_TIMER_STOP              0x1C
 #define JZ_REG_TIMER_STOP_SET          0x2C
@@ -97,12 +98,12 @@ static void jz4740_init_timer(void)
 static void jz4740_timer_enable(unsigned int timer)
 {
        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
-       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+       writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
 }
 
 static void jz4740_timer_disable(unsigned int timer)
 {
-       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+       writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
 }
 
@@ -216,7 +217,6 @@ void __init plat_time_init(void)
 {
     int ret;
        uint32_t clk_rate;
-       struct clk *ext_clk;
 
        jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
 
@@ -225,13 +225,7 @@ void __init plat_time_init(void)
            return;
        }
 
-       /*ext_clk = clk_get(NULL, "ext");
-       clk_rate = clk_get_rate(ext_clk) >> 4;
-       clk_put(ext_clk);*/
-
-
-       clk_rate = JZ_EXTAL >> 4;
-
+       clk_rate = jz4740_clock_bdata.ext_rate >> 4;
     jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
 
        clockevent_set_clock(&jz4740_clockevent, clk_rate);