target/linux/ipq806x/patches-5.15/116-v6.0-01-mtd-nand-raw-qcom_nandc-reorder-qcom_nand_host-struc.patch

   1 From b360514edb4743cbf86fc377699c75e98b1264c7 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Thu, 16 Jun 2022 02:18:33 +0200
   4 Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct
   5
   6 Reorder structs in nandc driver to save holes.
   7
   8 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
   9 Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
  10 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  11 Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-2-ansuelsmth@gmail.com
  12 ---
  13  drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++-------------
  14  1 file changed, 62 insertions(+), 45 deletions(-)
  15
  16 --- a/drivers/mtd/nand/raw/qcom_nandc.c
  17 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
  18 @@ -237,6 +237,9 @@ nandc_set_reg(chip, reg,                    \
  19   * @bam_ce - the array of BAM command elements
  20   * @cmd_sgl - sgl for NAND BAM command pipe
  21   * @data_sgl - sgl for NAND BAM consumer/producer pipe
  22 + * @last_data_desc - last DMA desc in data channel (tx/rx).
  23 + * @last_cmd_desc - last DMA desc in command channel.
  24 + * @txn_done - completion for NAND transfer.
  25   * @bam_ce_pos - the index in bam_ce which is available for next sgl
  26   * @bam_ce_start - the index in bam_ce which marks the start position ce
  27   *                for current sgl. It will be used for size calculation
  28 @@ -249,14 +252,14 @@ nandc_set_reg(chip, reg,                  \
  29   * @rx_sgl_start - start index in data sgl for rx.
  30   * @wait_second_completion - wait for second DMA desc completion before making
  31   *                          the NAND transfer completion.
  32 - * @txn_done - completion for NAND transfer.
  33 - * @last_data_desc - last DMA desc in data channel (tx/rx).
  34 - * @last_cmd_desc - last DMA desc in command channel.
  35   */
  36  struct bam_transaction {
  37         struct bam_cmd_element *bam_ce;
  38         struct scatterlist *cmd_sgl;
  39         struct scatterlist *data_sgl;
  40 +       struct dma_async_tx_descriptor *last_data_desc;
  41 +       struct dma_async_tx_descriptor *last_cmd_desc;
  42 +       struct completion txn_done;
  43         u32 bam_ce_pos;
  44         u32 bam_ce_start;
  45         u32 cmd_sgl_pos;
  46 @@ -266,25 +269,23 @@ struct bam_transaction {
  47         u32 rx_sgl_pos;
  48         u32 rx_sgl_start;
  49         bool wait_second_completion;
  50 -       struct completion txn_done;
  51 -       struct dma_async_tx_descriptor *last_data_desc;
  52 -       struct dma_async_tx_descriptor *last_cmd_desc;
  53  };
  54
  55  /*
  56   * This data type corresponds to the nand dma descriptor
  57 + * @dma_desc - low level DMA engine descriptor
  58   * @list - list for desc_info
  59 - * @dir - DMA transfer direction
  60 + *
  61   * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
  62   *           ADM
  63   * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
  64   * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
  65 - * @dma_desc - low level DMA engine descriptor
  66 + * @dir - DMA transfer direction
  67   */
  68  struct desc_info {
  69 +       struct dma_async_tx_descriptor *dma_desc;
  70         struct list_head node;
  71
  72 -       enum dma_data_direction dir;
  73         union {
  74                 struct scatterlist adm_sgl;
  75                 struct {
  76 @@ -292,7 +293,7 @@ struct desc_info {
  77                         int sgl_cnt;
  78                 };
  79         };
  80 -       struct dma_async_tx_descriptor *dma_desc;
  81 +       enum dma_data_direction dir;
  82  };
  83
  84  /*
  85 @@ -336,52 +337,64 @@ struct nandc_regs {
  86  /*
  87   * NAND controller data struct
  88   *
  89 - * @controller:                        base controller structure
  90 - * @host_list:                 list containing all the chips attached to the
  91 - *                             controller
  92   * @dev:                       parent device
  93 + *
  94   * @base:                      MMIO base
  95 - * @base_phys:                 physical base address of controller registers
  96 - * @base_dma:                  dma base address of controller registers
  97 + *
  98   * @core_clk:                  controller clock
  99   * @aon_clk:                   another controller clock
 100   *
 101 + * @regs:                      a contiguous chunk of memory for DMA register
 102 + *                             writes. contains the register values to be
 103 + *                             written to controller
 104 + *
 105 + * @props:                     properties of current NAND controller,
 106 + *                             initialized via DT match data
 107 + *
 108 + * @controller:                        base controller structure
 109 + * @host_list:                 list containing all the chips attached to the
 110 + *                             controller
 111 + *
 112   * @chan:                      dma channel
 113   * @cmd_crci:                  ADM DMA CRCI for command flow control
 114   * @data_crci:                 ADM DMA CRCI for data flow control
 115 + *
 116   * @desc_list:                 DMA descriptor list (list of desc_infos)
 117   *
 118   * @data_buffer:               our local DMA buffer for page read/writes,
 119   *                             used when we can't use the buffer provided
 120   *                             by upper layers directly
 121 - * @buf_size/count/start:      markers for chip->legacy.read_buf/write_buf
 122 - *                             functions
 123   * @reg_read_buf:              local buffer for reading back registers via DMA
 124 + *
 125 + * @base_phys:                 physical base address of controller registers
 126 + * @base_dma:                  dma base address of controller registers
 127   * @reg_read_dma:              contains dma address for register read buffer
 128 - * @reg_read_pos:              marker for data read in reg_read_buf
 129   *
 130 - * @regs:                      a contiguous chunk of memory for DMA register
 131 - *                             writes. contains the register values to be
 132 - *                             written to controller
 133 - * @cmd1/vld:                  some fixed controller register values
 134 - * @props:                     properties of current NAND controller,
 135 - *                             initialized via DT match data
 136 + * @buf_size/count/start:      markers for chip->legacy.read_buf/write_buf
 137 + *                             functions
 138   * @max_cwperpage:             maximum QPIC codewords required. calculated
 139   *                             from all connected NAND devices pagesize
 140 + *
 141 + * @reg_read_pos:              marker for data read in reg_read_buf
 142 + *
 143 + * @cmd1/vld:                  some fixed controller register values
 144   */
 145  struct qcom_nand_controller {
 146 -       struct nand_controller controller;
 147 -       struct list_head host_list;
 148 -
 149         struct device *dev;
 150
 151         void __iomem *base;
 152 -       phys_addr_t base_phys;
 153 -       dma_addr_t base_dma;
 154
 155         struct clk *core_clk;
 156         struct clk *aon_clk;
 157
 158 +       struct nandc_regs *regs;
 159 +       struct bam_transaction *bam_txn;
 160 +
 161 +       const struct qcom_nandc_props *props;
 162 +
 163 +       struct nand_controller controller;
 164 +       struct list_head host_list;
 165 +
 166         union {
 167                 /* will be used only by QPIC for BAM DMA */
 168                 struct {
 169 @@ -399,22 +412,22 @@ struct qcom_nand_controller {
 170         };
 171
 172         struct list_head desc_list;
 173 -       struct bam_transaction *bam_txn;
 174
 175         u8              *data_buffer;
 176 +       __le32          *reg_read_buf;
 177 +
 178 +       phys_addr_t base_phys;
 179 +       dma_addr_t base_dma;
 180 +       dma_addr_t reg_read_dma;
 181 +
 182         int             buf_size;
 183         int             buf_count;
 184         int             buf_start;
 185         unsigned int    max_cwperpage;
 186
 187 -       __le32 *reg_read_buf;
 188 -       dma_addr_t reg_read_dma;
 189         int reg_read_pos;
 190
 191 -       struct nandc_regs *regs;
 192 -
 193         u32 cmd1, vld;
 194 -       const struct qcom_nandc_props *props;
 195  };
 196
 197  /*
 198 @@ -430,19 +443,21 @@ struct qcom_nand_controller {
 199   *                             and reserved bytes
 200   * @cw_data:                   the number of bytes within a codeword protected
 201   *                             by ECC
 202 - * @use_ecc:                   request the controller to use ECC for the
 203 - *                             upcoming read/write
 204 - * @bch_enabled:               flag to tell whether BCH ECC mode is used
 205   * @ecc_bytes_hw:              ECC bytes used by controller hardware for this
 206   *                             chip
 207 - * @status:                    value to be returned if NAND_CMD_STATUS command
 208 - *                             is executed
 209 + *
 210   * @last_command:              keeps track of last command on this chip. used
 211   *                             for reading correct status
 212   *
 213   * @cfg0, cfg1, cfg0_raw..:    NANDc register configurations needed for
 214   *                             ecc/non-ecc mode for the current nand flash
 215   *                             device
 216 + *
 217 + * @status:                    value to be returned if NAND_CMD_STATUS command
 218 + *                             is executed
 219 + * @use_ecc:                   request the controller to use ECC for the
 220 + *                             upcoming read/write
 221 + * @bch_enabled:               flag to tell whether BCH ECC mode is used
 222   */
 223  struct qcom_nand_host {
 224         struct nand_chip chip;
 225 @@ -451,12 +466,10 @@ struct qcom_nand_host {
 226         int cs;
 227         int cw_size;
 228         int cw_data;
 229 -       bool use_ecc;
 230 -       bool bch_enabled;
 231         int ecc_bytes_hw;
 232         int spare_bytes;
 233         int bbm_size;
 234 -       u8 status;
 235 +
 236         int last_command;
 237
 238         u32 cfg0, cfg1;
 239 @@ -465,23 +478,27 @@ struct qcom_nand_host {
 240         u32 ecc_bch_cfg;
 241         u32 clrflashstatus;
 242         u32 clrreadstatus;
 243 +
 244 +       u8 status;
 245 +       bool use_ecc;
 246 +       bool bch_enabled;
 247  };
 248
 249  /*
 250   * This data type corresponds to the NAND controller properties which varies
 251   * among different NAND controllers.
 252   * @ecc_modes - ecc mode for NAND
 253 + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
 254   * @is_bam - whether NAND controller is using BAM
 255   * @is_qpic - whether NAND CTRL is part of qpic IP
 256   * @qpic_v2 - flag to indicate QPIC IP version 2
 257 - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
 258   */
 259  struct qcom_nandc_props {
 260         u32 ecc_modes;
 261 +       u32 dev_cmd_reg_start;
 262         bool is_bam;
 263         bool is_qpic;
 264         bool qpic_v2;
 265 -       u32 dev_cmd_reg_start;
 266  };
 267
 268  /* Frees the BAM transaction memory */