target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _RTL838X_ETH_H
   4 #define _RTL838X_ETH_H
   5
   6 /*
   7  * Register definition
   8  */
   9
  10 /* Per port MAC control */
  11 #define RTL838X_MAC_PORT_CTRL                   (0xd560)
  12 #define RTL839X_MAC_PORT_CTRL                   (0x8004)
  13 #define RTL930X_MAC_L2_PORT_CTRL                (0x3268)
  14 #define RTL930X_MAC_PORT_CTRL                   (0x3260)
  15 #define RTL931X_MAC_L2_PORT_CTRL                (0x6000)
  16 #define RTL931X_MAC_PORT_CTRL                   (0x6004)
  17
  18 /* DMA interrupt control and status registers */
  19 #define RTL838X_DMA_IF_CTRL                     (0x9f58)
  20 #define RTL838X_DMA_IF_INTR_STS                 (0x9f54)
  21 #define RTL838X_DMA_IF_INTR_MSK                 (0x9f50)
  22
  23 #define RTL839X_DMA_IF_CTRL                     (0x786c)
  24 #define RTL839X_DMA_IF_INTR_STS                 (0x7868)
  25 #define RTL839X_DMA_IF_INTR_MSK                 (0x7864)
  26
  27 #define RTL930X_DMA_IF_CTRL                     (0xe028)
  28 #define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS       (0xe01C)
  29 #define RTL930X_DMA_IF_INTR_RX_DONE_STS         (0xe020)
  30 #define RTL930X_DMA_IF_INTR_TX_DONE_STS         (0xe024)
  31 #define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK       (0xe010)
  32 #define RTL930X_DMA_IF_INTR_RX_DONE_MSK         (0xe014)
  33 #define RTL930X_DMA_IF_INTR_TX_DONE_MSK         (0xe018)
  34 #define RTL930X_L2_NTFY_IF_INTR_MSK             (0xe04C)
  35 #define RTL930X_L2_NTFY_IF_INTR_STS             (0xe050)
  36
  37 /* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
  38 #define RTL931X_DMA_IF_CTRL                     (0x0928)
  39 #define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS       (0x091c)
  40 #define RTL931X_DMA_IF_INTR_RX_DONE_STS         (0x0920)
  41 #define RTL931X_DMA_IF_INTR_TX_DONE_STS         (0x0924)
  42 #define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK       (0x0910)
  43 #define RTL931X_DMA_IF_INTR_RX_DONE_MSK         (0x0914)
  44 #define RTL931X_DMA_IF_INTR_TX_DONE_MSK         (0x0918)
  45 #define RTL931X_L2_NTFY_IF_INTR_MSK             (0x09E4)
  46 #define RTL931X_L2_NTFY_IF_INTR_STS             (0x09E8)
  47
  48 #define RTL838X_MAC_FORCE_MODE_CTRL             (0xa104)
  49 #define RTL839X_MAC_FORCE_MODE_CTRL             (0x02bc)
  50 #define RTL930X_MAC_FORCE_MODE_CTRL             (0xCA1C)
  51 #define RTL931X_MAC_FORCE_MODE_CTRL             (0x0ddc)
  52
  53 /* MAC address settings */
  54 #define RTL838X_MAC                             (0xa9ec)
  55 #define RTL839X_MAC                             (0x02b4)
  56 #define RTL838X_MAC_ALE                         (0x6b04)
  57 #define RTL838X_MAC2                            (0xa320)
  58 #define RTL930X_MAC_L2_ADDR_CTRL                (0xC714)
  59 #define RTL931X_MAC_L2_ADDR_CTRL                (0x135c)
  60
  61 /* Ringbuffer setup */
  62 #define RTL838X_DMA_RX_BASE                     (0x9f00)
  63 #define RTL839X_DMA_RX_BASE                     (0x780c)
  64 #define RTL930X_DMA_RX_BASE                     (0xdf00)
  65 #define RTL931X_DMA_RX_BASE                     (0x0800)
  66
  67 #define RTL838X_DMA_TX_BASE                     (0x9f40)
  68 #define RTL839X_DMA_TX_BASE                     (0x784c)
  69 #define RTL930X_DMA_TX_BASE                     (0xe000)
  70 #define RTL931X_DMA_TX_BASE                     (0x0900)
  71
  72 #define RTL838X_DMA_IF_RX_RING_SIZE             (0xB7E4)
  73 #define RTL839X_DMA_IF_RX_RING_SIZE             (0x6038)
  74 #define RTL930X_DMA_IF_RX_RING_SIZE             (0x7C60)
  75 #define RTL931X_DMA_IF_RX_RING_SIZE             (0x2080)
  76
  77 #define RTL838X_DMA_IF_RX_RING_CNTR             (0xB7E8)
  78 #define RTL839X_DMA_IF_RX_RING_CNTR             (0x603c)
  79 #define RTL930X_DMA_IF_RX_RING_CNTR             (0x7C8C)
  80 #define RTL931X_DMA_IF_RX_RING_CNTR             (0x20AC)
  81
  82 #define RTL838X_DMA_IF_RX_CUR                   (0x9F20)
  83 #define RTL839X_DMA_IF_RX_CUR                   (0x782c)
  84 #define RTL930X_DMA_IF_RX_CUR                   (0xdf80)
  85 #define RTL931X_DMA_IF_RX_CUR                   (0x0880)
  86
  87 #define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL    (0x9F48)
  88 #define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL    (0xE008)
  89
  90 #define RTL838X_DMY_REG31                       (0x3b28)
  91 #define RTL838X_SDS_MODE_SEL                    (0x0028)
  92 #define RTL838X_SDS_CFG_REG                     (0x0034)
  93 #define RTL838X_INT_MODE_CTRL                   (0x005c)
  94 #define RTL838X_CHIP_INFO                       (0x00d8)
  95 #define RTL838X_SDS4_REG28                      (0xef80)
  96 #define RTL838X_SDS4_DUMMY0                     (0xef8c)
  97 #define RTL838X_SDS5_EXT_REG6                   (0xf18c)
  98
  99 /* L2 features */
 100 #define RTL839X_TBL_ACCESS_L2_CTRL              (0x1180)
 101 #define RTL839X_TBL_ACCESS_L2_DATA(idx)         (0x1184 + ((idx) << 2))
 102 #define RTL838X_TBL_ACCESS_CTRL_0               (0x6914)
 103 #define RTL838X_TBL_ACCESS_DATA_0(idx)          (0x6918 + ((idx) << 2))
 104
 105 /* MAC-side link state handling */
 106 #define RTL838X_MAC_LINK_STS                    (0xa188)
 107 #define RTL839X_MAC_LINK_STS                    (0x0390)
 108 #define RTL930X_MAC_LINK_STS                    (0xCB10)
 109 #define RTL931X_MAC_LINK_STS                    (0x0ec0)
 110
 111 #define RTL838X_MAC_LINK_SPD_STS                (0xa190)
 112 #define RTL839X_MAC_LINK_SPD_STS                (0x03a0)
 113 #define RTL930X_MAC_LINK_SPD_STS                (0xCB18)
 114 #define RTL931X_MAC_LINK_SPD_STS                (0x0ed0)
 115
 116 #define RTL838X_MAC_LINK_DUP_STS                (0xa19c)
 117 #define RTL839X_MAC_LINK_DUP_STS                (0x03b0)
 118 #define RTL930X_MAC_LINK_DUP_STS                (0xCB28)
 119 #define RTL931X_MAC_LINK_DUP_STS                (0x0ef0)
 120
 121 // TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
 122
 123 #define RTL838X_MAC_TX_PAUSE_STS                (0xa1a0)
 124 #define RTL839X_MAC_TX_PAUSE_STS                (0x03b8)
 125 #define RTL930X_MAC_TX_PAUSE_STS                (0xCB2C)
 126 #define RTL931X_MAC_TX_PAUSE_STS                (0x0ef8)
 127
 128 #define RTL838X_MAC_RX_PAUSE_STS                (0xa1a4)
 129 #define RTL839X_MAC_RX_PAUSE_STS                (0xCB30)
 130 #define RTL930X_MAC_RX_PAUSE_STS                (0xC2F8)
 131 #define RTL931X_MAC_RX_PAUSE_STS                (0x0f00)
 132
 133 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL          (0xaa04)
 134 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL        (0xaa08)
 135
 136 #define RTL930X_L2_UNKN_UC_FLD_PMSK             (0x9064)
 137
 138 #define RTL839X_MAC_GLB_CTRL                    (0x02a8)
 139 #define RTL839X_SCHED_LB_TICK_TKN_CTRL          (0x60f8)
 140
 141 #define RTL838X_L2_TBL_FLUSH_CTRL               (0x3370)
 142 #define RTL839X_L2_TBL_FLUSH_CTRL               (0x3ba0)
 143 #define RTL930X_L2_TBL_FLUSH_CTRL               (0x9404)
 144 #define RTL931X_L2_TBL_FLUSH_CTRL               (0xCD9C)
 145
 146 #define RTL930X_L2_PORT_SABLK_CTRL              (0x905c)
 147 #define RTL930X_L2_PORT_DABLK_CTRL              (0x9060)
 148
 149 /* MAC link state bits */
 150 #define FORCE_EN                                (1 << 0)
 151 #define FORCE_LINK_EN                           (1 << 1)
 152 #define NWAY_EN                                 (1 << 2)
 153 #define DUPLX_MODE                              (1 << 3)
 154 #define TX_PAUSE_EN                             (1 << 6)
 155 #define RX_PAUSE_EN                             (1 << 7)
 156
 157 /* L2 Notification DMA interface */
 158 #define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C)
 159 #define RTL839X_L2_NOTIFICATION_CTRL            (0x7808)
 160 #define RTL931X_L2_NTFY_RING_BASE_ADDR          (0x09DC)
 161 #define RTL931X_L2_NTFY_RING_CUR_ADDR           (0x09E0)
 162 #define RTL839X_L2_NOTIFICATION_CTRL            (0x7808)
 163 #define RTL931X_L2_NTFY_CTRL                    (0xCDC8)
 164 #define RTL838X_L2_CTRL_0                       (0x3200)
 165 #define RTL839X_L2_CTRL_0                       (0x3800)
 166 #define RTL930X_L2_CTRL                         (0x8FD8)
 167 #define RTL931X_L2_CTRL                         (0xC800)
 168
 169 /* TRAPPING to CPU-PORT */
 170 #define RTL838X_SPCL_TRAP_IGMP_CTRL             (0x6984)
 171 #define RTL838X_RMA_CTRL_0                      (0x4300)
 172 #define RTL838X_RMA_CTRL_1                      (0x4304)
 173 #define RTL839X_RMA_CTRL_0                      (0x1200)
 174
 175 #define RTL839X_SPCL_TRAP_IGMP_CTRL             (0x1058)
 176 #define RTL839X_RMA_CTRL_1                      (0x1204)
 177 #define RTL839X_RMA_CTRL_2                      (0x1208)
 178 #define RTL839X_RMA_CTRL_3                      (0x120C)
 179
 180 #define RTL930X_RMA_CTRL_0                      (0x9E60)
 181 #define RTL930X_RMA_CTRL_1                      (0x9E64)
 182 #define RTL930X_RMA_CTRL_2                      (0x9E68)
 183
 184 #define RTL931X_RMA_CTRL_0                      (0x8800)
 185 #define RTL931X_RMA_CTRL_1                      (0x8804)
 186 #define RTL931X_RMA_CTRL_2                      (0x8808)
 187
 188 /* Advanced SMI control for clause 45 PHYs */
 189 #define RTL930X_SMI_MAC_TYPE_CTRL               (0xCA04)
 190 #define RTL930X_SMI_PORT24_27_ADDR_CTRL         (0xCB90)
 191 #define RTL930X_SMI_PORT0_15_POLLING_SEL        (0xCA08)
 192 #define RTL930X_SMI_PORT16_27_POLLING_SEL       (0xCA0C)
 193
 194 /* Registers of the internal Serdes of the 8390 */
 195 #define RTL839X_SDS12_13_XSG0                   (0xB800)
 196
 197 /* Registers of the internal Serdes of the 8380 */
 198 #define RTL838X_SDS4_FIB_REG0                   (0xF800)
 199
 200 inline int rtl838x_mac_port_ctrl(int p)
 201 {
 202         return RTL838X_MAC_PORT_CTRL + (p << 7);
 203 }
 204
 205 inline int rtl839x_mac_port_ctrl(int p)
 206 {
 207         return RTL839X_MAC_PORT_CTRL + (p << 7);
 208 }
 209
 210 /* On the RTL931XX, the functionality of the MAC port control register is split up
 211  * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used
 212  * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL
 213  */
 214
 215 inline int rtl930x_mac_port_ctrl(int p)
 216 {
 217         return RTL930X_MAC_L2_PORT_CTRL + (p << 6);
 218 }
 219
 220 inline int rtl931x_mac_port_ctrl(int p)
 221 {
 222         return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
 223 }
 224
 225 inline int rtl838x_dma_if_rx_ring_size(int i)
 226 {
 227         return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
 228 }
 229
 230 inline int rtl839x_dma_if_rx_ring_size(int i)
 231 {
 232         return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
 233 }
 234
 235 inline int rtl930x_dma_if_rx_ring_size(int i)
 236 {
 237         return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
 238 }
 239
 240 inline int rtl931x_dma_if_rx_ring_size(int i)
 241 {
 242         return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
 243 }
 244
 245 inline int rtl838x_dma_if_rx_ring_cntr(int i)
 246 {
 247         return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
 248 }
 249
 250 inline int rtl839x_dma_if_rx_ring_cntr(int i)
 251 {
 252         return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
 253 }
 254
 255 inline int rtl930x_dma_if_rx_ring_cntr(int i)
 256 {
 257         return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
 258 }
 259
 260 inline int rtl931x_dma_if_rx_ring_cntr(int i)
 261 {
 262         return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
 263 }
 264
 265 inline u32 rtl838x_get_mac_link_sts(int port)
 266 {
 267         return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));
 268 }
 269
 270 inline u32 rtl839x_get_mac_link_sts(int p)
 271 {
 272         return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
 273 }
 274
 275 inline u32 rtl930x_get_mac_link_sts(int port)
 276 {
 277         return (sw_r32(RTL930X_MAC_LINK_STS) & BIT(port));
 278 }
 279
 280 inline u32 rtl931x_get_mac_link_sts(int p)
 281 {
 282         return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
 283 }
 284
 285 inline u32 rtl838x_get_mac_link_dup_sts(int port)
 286 {
 287         return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));
 288 }
 289
 290 inline u32 rtl839x_get_mac_link_dup_sts(int p)
 291 {
 292         return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
 293 }
 294
 295 inline u32 rtl930x_get_mac_link_dup_sts(int port)
 296 {
 297         return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));
 298 }
 299
 300 inline u32 rtl931x_get_mac_link_dup_sts(int p)
 301 {
 302         return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
 303 }
 304
 305 inline u32 rtl838x_get_mac_link_spd_sts(int port)
 306 {
 307         int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
 308         u32 speed = sw_r32(r);
 309
 310         speed >>= (port % 16) << 1;
 311         return (speed & 0x3);
 312 }
 313
 314 inline u32 rtl839x_get_mac_link_spd_sts(int port)
 315 {
 316         int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
 317         u32 speed = sw_r32(r);
 318
 319         speed >>= (port % 16) << 1;
 320         return (speed & 0x3);
 321 }
 322
 323
 324 inline u32 rtl930x_get_mac_link_spd_sts(int port)
 325 {
 326         int r = RTL930X_MAC_LINK_SPD_STS + ((port / 10) << 2);
 327         u32 speed = sw_r32(r);
 328
 329         speed >>= (port % 10) * 3;
 330         return (speed & 0x7);
 331 }
 332
 333 inline u32 rtl931x_get_mac_link_spd_sts(int port)
 334 {
 335         int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
 336         u32 speed = sw_r32(r);
 337
 338         speed >>= (port % 8) << 2;
 339         return (speed & 0xf);
 340 }
 341
 342 inline u32 rtl838x_get_mac_rx_pause_sts(int port)
 343 {
 344         return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
 345 }
 346
 347 inline u32 rtl839x_get_mac_rx_pause_sts(int p)
 348 {
 349         return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 350 }
 351
 352 inline u32 rtl930x_get_mac_rx_pause_sts(int port)
 353 {
 354         return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));
 355 }
 356
 357 inline u32 rtl931x_get_mac_rx_pause_sts(int p)
 358 {
 359         return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 360 }
 361
 362 inline u32 rtl838x_get_mac_tx_pause_sts(int port)
 363 {
 364         return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
 365 }
 366
 367 inline u32 rtl839x_get_mac_tx_pause_sts(int p)
 368 {
 369         return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 370 }
 371
 372 inline u32 rtl930x_get_mac_tx_pause_sts(int port)
 373 {
 374         return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));
 375 }
 376
 377 inline u32 rtl931x_get_mac_tx_pause_sts(int p)
 378 {
 379         return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
 380 }
 381
 382 struct p_hdr;
 383 struct dsa_tag;
 384
 385 struct rtl838x_reg {
 386         irqreturn_t (*net_irq)(int irq, void *dev_id);
 387         int (*mac_port_ctrl)(int port);
 388         int dma_if_intr_sts;
 389         int dma_if_intr_msk;
 390         int dma_if_intr_rx_runout_sts;
 391         int dma_if_intr_rx_done_sts;
 392         int dma_if_intr_tx_done_sts;
 393         int dma_if_intr_rx_runout_msk;
 394         int dma_if_intr_rx_done_msk;
 395         int dma_if_intr_tx_done_msk;
 396         int l2_ntfy_if_intr_sts;
 397         int l2_ntfy_if_intr_msk;
 398         int dma_if_ctrl;
 399         int mac_force_mode_ctrl;
 400         int dma_rx_base;
 401         int dma_tx_base;
 402         int (*dma_if_rx_ring_size)(int ring);
 403         int (*dma_if_rx_ring_cntr)(int ring);
 404         int dma_if_rx_cur;
 405         int rst_glb_ctrl;
 406         u32 (*get_mac_link_sts)(int port);
 407         u32 (*get_mac_link_dup_sts)(int port);
 408         u32 (*get_mac_link_spd_sts)(int port);
 409         u32 (*get_mac_rx_pause_sts)(int port);
 410         u32 (*get_mac_tx_pause_sts)(int port);
 411         int mac;
 412         int l2_tbl_flush_ctrl;
 413         void (*update_cntr)(int r, int work_done);
 414         void (*create_tx_header)(struct p_hdr *h, int dest_port, int prio);
 415         bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
 416 };
 417
 418 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 419 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 420 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 421 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 422 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 423 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 424 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 425 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 426 void rtl9300_sds_power(int sds_num, int val);
 427
 428 #endif /* _RTL838X_ETH_H */