package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch

   1 --- /dev/null
   2 +++ b/board/arcadyan/vgv7519/Makefile
   3 @@ -0,0 +1,27 @@
   4 +#
   5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
   6 +#
   7 +# SPDX-License-Identifier:     GPL-2.0+
   8 +#
   9 +
  10 +include $(TOPDIR)/config.mk
  11 +
  12 +LIB    = $(obj)lib$(BOARD).o
  13 +
  14 +COBJS  = $(BOARD).o
  15 +
  16 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  17 +OBJS   := $(addprefix $(obj),$(COBJS))
  18 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  19 +
  20 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  21 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  22 +
  23 +#########################################################################
  24 +
  25 +# defines $(obj).depend target
  26 +include $(SRCTREE)/rules.mk
  27 +
  28 +sinclude $(obj).depend
  29 +
  30 +#########################################################################
  31 --- /dev/null
  32 +++ b/board/arcadyan/vgv7519/config.mk
  33 @@ -0,0 +1,7 @@
  34 +#
  35 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
  36 +#
  37 +# SPDX-License-Identifier:     GPL-2.0+
  38 +#
  39 +
  40 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
  41 --- /dev/null
  42 +++ b/board/arcadyan/vgv7519/ddr_settings.h
  43 @@ -0,0 +1,70 @@
  44 +/*
  45 + * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
  46 + *
  47 + * The values have been extracted from original brnboot.
  48 + *
  49 + * SPDX-License-Identifier:    GPL-2.0+
  50 + */
  51 +
  52 +#define        MC_CCR00_VALUE  0x101
  53 +#define        MC_CCR01_VALUE  0x1000100
  54 +#define        MC_CCR02_VALUE  0x1010000
  55 +#define        MC_CCR03_VALUE  0x100
  56 +#define        MC_CCR04_VALUE  0x1000000
  57 +#define        MC_CCR05_VALUE  0x1000101
  58 +#define        MC_CCR06_VALUE  0x1000100
  59 +#define        MC_CCR07_VALUE  0x1010000
  60 +#define        MC_CCR08_VALUE  0x1000101
  61 +#define        MC_CCR09_VALUE  0x0
  62 +#define        MC_CCR10_VALUE  0x2000100
  63 +#define        MC_CCR11_VALUE  0x2000401
  64 +#define        MC_CCR12_VALUE  0x30000
  65 +#define        MC_CCR13_VALUE  0x202
  66 +#define        MC_CCR14_VALUE  0x7080A0F
  67 +#define        MC_CCR15_VALUE  0x2040F
  68 +#define        MC_CCR16_VALUE  0x40000
  69 +#define        MC_CCR17_VALUE  0x70102
  70 +#define        MC_CCR18_VALUE  0x4020002
  71 +#define        MC_CCR19_VALUE  0x30302
  72 +#define        MC_CCR20_VALUE  0x8000700
  73 +#define        MC_CCR21_VALUE  0x40F020A
  74 +#define        MC_CCR22_VALUE  0x0
  75 +#define        MC_CCR23_VALUE  0xC020000
  76 +#define        MC_CCR24_VALUE  0x4401B04
  77 +#define        MC_CCR25_VALUE  0x0
  78 +#define        MC_CCR26_VALUE  0x0
  79 +#define        MC_CCR27_VALUE  0x6420000
  80 +#define        MC_CCR28_VALUE  0x0
  81 +#define        MC_CCR29_VALUE  0x0
  82 +#define        MC_CCR30_VALUE  0x798
  83 +#define        MC_CCR31_VALUE  0x2040F
  84 +#define        MC_CCR32_VALUE  0x0
  85 +#define        MC_CCR33_VALUE  0x650000
  86 +#define        MC_CCR34_VALUE  0x200C8
  87 +#define        MC_CCR35_VALUE  0x1D445D
  88 +#define        MC_CCR36_VALUE  0xC8
  89 +#define        MC_CCR37_VALUE  0xC351
  90 +#define        MC_CCR38_VALUE  0x0
  91 +#define        MC_CCR39_VALUE  0x141F04
  92 +#define        MC_CCR40_VALUE  0x142704
  93 +#define        MC_CCR41_VALUE  0x141B42
  94 +#define        MC_CCR42_VALUE  0x141B42
  95 +#define        MC_CCR43_VALUE  0x566504
  96 +#define        MC_CCR44_VALUE  0x566504
  97 +#define        MC_CCR45_VALUE  0x565F17
  98 +#define        MC_CCR46_VALUE  0x565F17
  99 +#define        MC_CCR47_VALUE  0x2040F
 100 +#define        MC_CCR48_VALUE  0x0
 101 +#define        MC_CCR49_VALUE  0x0
 102 +#define        MC_CCR50_VALUE  0x0
 103 +#define        MC_CCR51_VALUE  0x0
 104 +#define        MC_CCR52_VALUE  0x133
 105 +#define        MC_CCR53_VALUE  0xF3014B27
 106 +#define        MC_CCR54_VALUE  0xF3014B27
 107 +#define        MC_CCR55_VALUE  0xF3014B27
 108 +#define        MC_CCR56_VALUE  0xF3014B27
 109 +#define        MC_CCR57_VALUE  0x7800301
 110 +#define        MC_CCR58_VALUE  0x7800301
 111 +#define        MC_CCR59_VALUE  0x7800301
 112 +#define        MC_CCR60_VALUE  0x7800301
 113 +#define        MC_CCR61_VALUE  0x4
 114 --- /dev/null
 115 +++ b/board/arcadyan/vgv7519/vgv7519.c
 116 @@ -0,0 +1,95 @@
 117 +/*
 118 + * This file is released under the terms of GPL v2 and any later version.
 119 + * See the file COPYING in the root directory of the source tree for details.
 120 + *
 121 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
 122 + */
 123 +
 124 +#include <common.h>
 125 +#include <asm/gpio.h>
 126 +#include <asm/lantiq/eth.h>
 127 +#include <asm/lantiq/chipid.h>
 128 +#include <asm/lantiq/cpu.h>
 129 +#include <asm/arch/gphy.h>
 130 +
 131 +#if defined(CONFIG_SYS_BOOT_RAM)
 132 +#define do_gpio_init   1
 133 +#define do_pll_init    0
 134 +#define do_dcdc_init   1
 135 +#elif defined(CONFIG_SYS_BOOT_NOR)
 136 +#define do_gpio_init   1
 137 +#define do_pll_init    1
 138 +#define do_dcdc_init   1
 139 +#else
 140 +#define do_gpio_init   0
 141 +#define do_pll_init    0
 142 +#define do_dcdc_init   1
 143 +#endif
 144 +
 145 +#define GPIO_GPHY_RESET        47
 146 +
 147 +static void gpio_init(void)
 148 +{
 149 +       /* Disable reset on external eth PHY */
 150 +       gpio_direction_output(GPIO_GPHY_RESET, 1);
 151 +}
 152 +
 153 +int board_early_init_f(void)
 154 +{
 155 +       if (do_gpio_init)
 156 +               gpio_init();
 157 +
 158 +       if (do_pll_init)
 159 +               ltq_pll_init();
 160 +
 161 +       if (do_dcdc_init)
 162 +               ltq_dcdc_init(0x7F);
 163 +
 164 +       return 0;
 165 +}
 166 +
 167 +int checkboard(void)
 168 +{
 169 +       puts("Board: " CONFIG_BOARD_NAME "\n");
 170 +       ltq_chip_print_info();
 171 +
 172 +       return 0;
 173 +}
 174 +
 175 +static const struct ltq_eth_port_config eth_port_config[] = {
 176 +       /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
 177 +       { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
 178 +       /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
 179 +       { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
 180 +       /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
 181 +       { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
 182 +       /* GMAC3: unused */
 183 +       { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
 184 +       /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
 185 +       { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
 186 +       /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
 187 +       { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
 188 +};
 189 +
 190 +static const struct ltq_eth_board_config eth_board_config = {
 191 +       .ports = eth_port_config,
 192 +       .num_ports = ARRAY_SIZE(eth_port_config),
 193 +};
 194 +
 195 +int board_eth_init(bd_t * bis)
 196 +{
 197 +       const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
 198 +       const ulong fw_addr = 0x80FF0000;
 199 +
 200 +       if (ltq_chip_version_get() == 1)
 201 +               ltq_gphy_phy22f_a1x_load(fw_addr);
 202 +       else
 203 +               ltq_gphy_phy22f_a2x_load(fw_addr);
 204 +
 205 +       ltq_cgu_gphy_clk_src(clk);
 206 +
 207 +       ltq_rcu_gphy_boot(0, fw_addr);
 208 +       ltq_rcu_gphy_boot(1, fw_addr);
 209 +
 210 +       return ltq_eth_initialize(&eth_board_config);
 211 +}
 212 --- a/boards.cfg
 213 +++ b/boards.cfg
 214 @@ -537,6 +537,9 @@ Active  mips        mips32         incai
 215  Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_brn                      vgv7510kw22:SYS_BOOT_BRN                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 216  Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_nor                      vgv7510kw22:SYS_BOOT_NOR                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 217  Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_ram                      vgv7510kw22:SYS_BOOT_RAM                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 218 +Active  mips        mips32         vrx200      arcadyan        vgv7519             vgv7519_brn                          vgv7519:SYS_BOOT_BRN                                                                                                              Mathias Kresin <dev@kresin.me>
 219 +Active  mips        mips32         vrx200      arcadyan        vgv7519             vgv7519_nor                          vgv7519:SYS_BOOT_NOR                                                                                                              Eddi De Pieri <eddi@depieri.net>
 220 +Active  mips        mips32         vrx200      arcadyan        vgv7519             vgv7519_ram                          vgv7519:SYS_BOOT_RAM                                                                                                              Eddi De Pieri <eddi@depieri.net>
 221  Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 222  Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 223  Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 224 --- /dev/null
 225 +++ b/include/configs/vgv7519.h
 226 @@ -0,0 +1,64 @@
 227 +/*
 228 + * This file is released under the terms of GPL v2 and any later version.
 229 + * See the file COPYING in the root directory of the source tree for details.
 230 + *
 231 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
 232 + */
 233 +
 234 +#ifndef __CONFIG_H
 235 +#define __CONFIG_H
 236 +
 237 +#define CONFIG_MACH_TYPE       "VGV7519"
 238 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 239 +#define CONFIG_BOARD_NAME      "Arcadyan VGV7519"
 240 +
 241 +/* Configure SoC */
 242 +#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */
 243 +
 244 +#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */
 245 +
 246 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */
 247 +
 248 +#define CONFIG_SYS_BOOTM_LEN           0x1000000       /* 16 MB */
 249 +
 250 +#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of memory banks */
 251 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH2_BASE }
 252 +
 253 +/* Environment */
 254 +#if defined(CONFIG_SYS_BOOT_BRN)
 255 +#define CONFIG_SYS_TEXT_BASE           0x80002000
 256 +#define CONFIG_SKIP_LOWLEVEL_INIT
 257 +#define CONFIG_SYS_DISABLE_CACHE
 258 +#define CONFIG_ENV_IS_NOWHERE
 259 +#define CONFIG_ENV_OVERWRITE           1
 260 +#elif defined(CONFIG_SYS_BOOT_NOR)
 261 +#define CONFIG_ENV_IS_IN_FLASH
 262 +#define CONFIG_ENV_OVERWRITE
 263 +#define CONFIG_ENV_OFFSET              (384 * 1024)
 264 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 265 +#else
 266 +#define CONFIG_ENV_IS_NOWHERE
 267 +#endif
 268 +
 269 +#define CONFIG_ENV_SIZE                        (8 * 1024)
 270 +
 271 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 272 +
 273 +/* Console */
 274 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 275 +#define CONFIG_BAUDRATE                        115200
 276 +#define CONFIG_CONSOLE_ASC             1
 277 +#define CONFIG_CONSOLE_DEV             "ttyLTQ1"
 278 +
 279 +/* Pull in default board configs for Lantiq XWAY VRX200 */
 280 +#include <asm/lantiq/config.h>
 281 +#include <asm/arch/config.h>
 282 +
 283 +/* Pull in default OpenWrt configs for Lantiq SoC */
 284 +#include "openwrt-lantiq-common.h"
 285 +
 286 +#define CONFIG_EXTRA_ENV_SETTINGS      \
 287 +       CONFIG_ENV_LANTIQ_DEFAULTS \
 288 +       "kernel_addr=0xB0080000\0"
 289 +
 290 +#endif /* __CONFIG_H */