1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_core.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
24 *******************************************************************************/
26 #define IFX_ATM_VER_MAJOR 1
27 #define IFX_ATM_VER_MID 0
28 #define IFX_ATM_VER_MINOR 26
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/proc_fs.h>
36 #include <linux/init.h>
37 #include <linux/ioctl.h>
38 #include <linux/atmdev.h>
39 #include <linux/platform_device.h>
40 #include <linux/of_device.h>
41 #include <linux/atm.h>
42 #include <linux/clk.h>
43 #include <linux/interrupt.h>
48 #include <lantiq_soc.h>
50 #include "ifxmips_atm_core.h"
52 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
53 #define MODULE_PARM(a, b) module_param(a, int, 0)
56 \brief QSB cell delay variation due to concurrency
58 static int qsb_tau
= 1; /* QSB cell delay variation due to concurrency */
60 \brief QSB scheduler burst length
62 static int qsb_srvm
= 0x0F; /* QSB scheduler burst length */
64 \brief QSB time step, all legal values are 1, 2, 4
66 static int qsb_tstep
= 4 ; /* QSB time step, all legal values are 1, 2, 4 */
69 \brief Write descriptor delay
71 static int write_descriptor_delay
= 0x20; /* Write descriptor delay */
74 \brief AAL5 padding byte ('~')
76 static int aal5_fill_pattern
= 0x007E; /* AAL5 padding byte ('~') */
78 \brief Max frame size for RX
80 static int aal5r_max_packet_size
= 0x0700; /* Max frame size for RX */
82 \brief Min frame size for RX
84 static int aal5r_min_packet_size
= 0x0000; /* Min frame size for RX */
86 \brief Max frame size for TX
88 static int aal5s_max_packet_size
= 0x0700; /* Max frame size for TX */
90 \brief Min frame size for TX
92 static int aal5s_min_packet_size
= 0x0000; /* Min frame size for TX */
94 \brief Drop error packet in RX path
96 static int aal5r_drop_error_packet
= 1; /* Drop error packet in RX path */
99 \brief Number of descriptors per DMA RX channel
101 static int dma_rx_descriptor_length
= 128; /* Number of descriptors per DMA RX channel */
103 \brief Number of descriptors per DMA TX channel
105 static int dma_tx_descriptor_length
= 64; /* Number of descriptors per DMA TX channel */
107 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
109 static int dma_rx_clp1_descriptor_threshold
= 38;
112 MODULE_PARM(qsb_tau
, "i");
113 MODULE_PARM_DESC(qsb_tau
, "Cell delay variation. Value must be > 0");
114 MODULE_PARM(qsb_srvm
, "i");
115 MODULE_PARM_DESC(qsb_srvm
, "Maximum burst size");
116 MODULE_PARM(qsb_tstep
, "i");
117 MODULE_PARM_DESC(qsb_tstep
, "n*32 cycles per sbs cycles n=1,2,4");
119 MODULE_PARM(write_descriptor_delay
, "i");
120 MODULE_PARM_DESC(write_descriptor_delay
, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
122 MODULE_PARM(aal5_fill_pattern
, "i");
123 MODULE_PARM_DESC(aal5_fill_pattern
, "Filling pattern (PAD) for AAL5 frames");
124 MODULE_PARM(aal5r_max_packet_size
, "i");
125 MODULE_PARM_DESC(aal5r_max_packet_size
, "Max packet size in byte for downstream AAL5 frames");
126 MODULE_PARM(aal5r_min_packet_size
, "i");
127 MODULE_PARM_DESC(aal5r_min_packet_size
, "Min packet size in byte for downstream AAL5 frames");
128 MODULE_PARM(aal5s_max_packet_size
, "i");
129 MODULE_PARM_DESC(aal5s_max_packet_size
, "Max packet size in byte for upstream AAL5 frames");
130 MODULE_PARM(aal5s_min_packet_size
, "i");
131 MODULE_PARM_DESC(aal5s_min_packet_size
, "Min packet size in byte for upstream AAL5 frames");
132 MODULE_PARM(aal5r_drop_error_packet
, "i");
133 MODULE_PARM_DESC(aal5r_drop_error_packet
, "Non-zero value to drop error packet for downstream");
135 MODULE_PARM(dma_rx_descriptor_length
, "i");
136 MODULE_PARM_DESC(dma_rx_descriptor_length
, "Number of descriptor assigned to DMA RX channel (>16)");
137 MODULE_PARM(dma_tx_descriptor_length
, "i");
138 MODULE_PARM_DESC(dma_tx_descriptor_length
, "Number of descriptor assigned to DMA TX channel (>16)");
139 MODULE_PARM(dma_rx_clp1_descriptor_threshold
, "i");
140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold
, "Descriptor threshold for cells with cell loss priority 1");
145 * ####################################
147 * ####################################
150 #ifdef CONFIG_AMAZON_SE
151 #define ENABLE_LESS_CACHE_INV 1
152 #define LESS_CACHE_INV_LEN 96
155 #define DUMP_SKB_LEN ~0
160 * ####################################
162 * ####################################
168 static int ppe_ioctl(struct atm_dev
*, unsigned int, void *);
169 static int ppe_open(struct atm_vcc
*);
170 static void ppe_close(struct atm_vcc
*);
171 static int ppe_send(struct atm_vcc
*, struct sk_buff
*);
172 static int ppe_send_oam(struct atm_vcc
*, void *, int);
173 static int ppe_change_qos(struct atm_vcc
*, struct atm_qos
*, int);
178 static inline void adsl_led_flash(void);
181 * 64-bit operation used by MIB calculation
183 static inline void u64_add_u32(ppe_u64_t
, unsigned int, ppe_u64_t
*);
186 * buffer manage functions
188 static inline struct sk_buff
* alloc_skb_rx(void);
189 static inline struct sk_buff
* alloc_skb_tx(unsigned int);
190 struct sk_buff
* atm_alloc_tx(struct atm_vcc
*, unsigned int);
191 static inline void atm_free_tx_skb_vcc(struct sk_buff
*, struct atm_vcc
*);
192 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int);
193 static inline int get_tx_desc(unsigned int);
196 * mailbox handler and signal function
198 static inline void mailbox_oam_rx_handler(void);
199 static inline void mailbox_aal_rx_handler(void);
200 static irqreturn_t
mailbox_irq_handler(int, void *);
201 static inline void mailbox_signal(unsigned int, int);
202 static void do_ppe_tasklet(unsigned long);
203 DECLARE_TASKLET(g_dma_tasklet
, do_ppe_tasklet
, 0);
206 * QSB & HTU setting functions
208 static void set_qsb(struct atm_vcc
*, struct atm_qos
*, unsigned int);
209 static void qsb_global_set(void);
210 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
211 static inline void clear_htu_entry(unsigned int);
212 static void validate_oam_htu_entry(void);
213 static void invalidate_oam_htu_entry(void);
216 * look up for connection ID
218 static inline int find_vpi(unsigned int);
219 static inline int find_vpivci(unsigned int, unsigned int);
220 static inline int find_vcc(struct atm_vcc
*);
222 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *);
225 * Init & clean-up functions
227 static inline void check_parameters(void);
228 static inline int init_priv_data(void);
229 static inline void clear_priv_data(void);
230 static inline void init_rx_tables(void);
231 static inline void init_tx_tables(void);
236 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
237 extern void ifx_push_oam(unsigned char *);
239 static inline void ifx_push_oam(unsigned char *dummy
) {}
242 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
243 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
244 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
246 extern int (*ifx_mei_atm_showtime_exit
)(void);
247 extern int ifx_mei_atm_led_blink(void);
249 static inline int ifx_mei_atm_led_blink(void) { return 0; }
250 static inline int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
)
252 if ( is_showtime
!= NULL
)
256 int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *) = NULL
;
257 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter
);
259 int (*ifx_mei_atm_showtime_exit
)(void) = NULL
;
260 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit
);
264 static struct sk_buff
* (*ifx_atm_alloc_tx
)(struct atm_vcc
*, unsigned int) = NULL
;
266 static struct atm_priv_data g_atm_priv_data
;
268 static struct atmdev_ops g_ifx_atm_ops
= {
273 .send_oam
= ppe_send_oam
,
274 .change_qos
= ppe_change_qos
,
275 .owner
= THIS_MODULE
,
278 static int g_showtime
= 0;
279 static void *g_xdata_addr
= NULL
;
281 static int ppe_ioctl(struct atm_dev
*dev
, unsigned int cmd
, void *arg
)
284 atm_cell_ifEntry_t mib_cell
;
285 atm_aal5_ifEntry_t mib_aal5
;
286 atm_aal5_vcc_x_t mib_vcc
;
290 if ( _IOC_TYPE(cmd
) != PPE_ATM_IOC_MAGIC
291 || _IOC_NR(cmd
) >= PPE_ATM_IOC_MAXNR
)
294 if ( _IOC_DIR(cmd
) & _IOC_READ
)
295 ret
= !access_ok(VERIFY_WRITE
, arg
, _IOC_SIZE(cmd
));
296 else if ( _IOC_DIR(cmd
) & _IOC_WRITE
)
297 ret
= !access_ok(VERIFY_READ
, arg
, _IOC_SIZE(cmd
));
302 case PPE_ATM_MIB_CELL
: /* cell level MIB */
303 /* These MIB should be read at ARC side, now put zero only. */
304 mib_cell
.ifHCInOctets_h
= 0;
305 mib_cell
.ifHCInOctets_l
= 0;
306 mib_cell
.ifHCOutOctets_h
= 0;
307 mib_cell
.ifHCOutOctets_l
= 0;
308 mib_cell
.ifInErrors
= 0;
309 mib_cell
.ifInUnknownProtos
= WAN_MIB_TABLE
->wrx_drophtu_cell
;
310 mib_cell
.ifOutErrors
= 0;
312 ret
= sizeof(mib_cell
) - copy_to_user(arg
, &mib_cell
, sizeof(mib_cell
));
315 case PPE_ATM_MIB_AAL5
: /* AAL5 MIB */
316 value
= WAN_MIB_TABLE
->wrx_total_byte
;
317 u64_add_u32(g_atm_priv_data
.wrx_total_byte
, value
- g_atm_priv_data
.prev_wrx_total_byte
, &g_atm_priv_data
.wrx_total_byte
);
318 g_atm_priv_data
.prev_wrx_total_byte
= value
;
319 mib_aal5
.ifHCInOctets_h
= g_atm_priv_data
.wrx_total_byte
.h
;
320 mib_aal5
.ifHCInOctets_l
= g_atm_priv_data
.wrx_total_byte
.l
;
322 value
= WAN_MIB_TABLE
->wtx_total_byte
;
323 u64_add_u32(g_atm_priv_data
.wtx_total_byte
, value
- g_atm_priv_data
.prev_wtx_total_byte
, &g_atm_priv_data
.wtx_total_byte
);
324 g_atm_priv_data
.prev_wtx_total_byte
= value
;
325 mib_aal5
.ifHCOutOctets_h
= g_atm_priv_data
.wtx_total_byte
.h
;
326 mib_aal5
.ifHCOutOctets_l
= g_atm_priv_data
.wtx_total_byte
.l
;
328 mib_aal5
.ifInUcastPkts
= g_atm_priv_data
.wrx_pdu
;
329 mib_aal5
.ifOutUcastPkts
= WAN_MIB_TABLE
->wtx_total_pdu
;
330 mib_aal5
.ifInErrors
= WAN_MIB_TABLE
->wrx_err_pdu
;
331 mib_aal5
.ifInDiscards
= WAN_MIB_TABLE
->wrx_dropdes_pdu
+ g_atm_priv_data
.wrx_drop_pdu
;
332 mib_aal5
.ifOutErros
= g_atm_priv_data
.wtx_err_pdu
;
333 mib_aal5
.ifOutDiscards
= g_atm_priv_data
.wtx_drop_pdu
;
335 ret
= sizeof(mib_aal5
) - copy_to_user(arg
, &mib_aal5
, sizeof(mib_aal5
));
338 case PPE_ATM_MIB_VCC
: /* VCC related MIB */
339 copy_from_user(&mib_vcc
, arg
, sizeof(mib_vcc
));
340 conn
= find_vpivci(mib_vcc
.vpi
, mib_vcc
.vci
);
342 mib_vcc
.mib_vcc
.aal5VccCrcErrors
= g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
;
343 mib_vcc
.mib_vcc
.aal5VccOverSizedSDUs
= g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
;
344 mib_vcc
.mib_vcc
.aal5VccSarTimeOuts
= 0; /* no timer support */
345 ret
= sizeof(mib_vcc
) - copy_to_user(arg
, &mib_vcc
, sizeof(mib_vcc
));
357 static int ppe_open(struct atm_vcc
*vcc
)
360 short vpi
= vcc
->vpi
;
362 struct port
*port
= &g_atm_priv_data
.port
[(int)vcc
->dev
->dev_data
];
364 int f_enable_irq
= 0;
366 if ( vcc
->qos
.aal
!= ATM_AAL5
&& vcc
->qos
.aal
!= ATM_AAL0
)
367 return -EPROTONOSUPPORT
;
369 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
370 /* check bandwidth */
371 if ( (vcc
->qos
.txtp
.traffic_class
== ATM_CBR
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
372 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_RT
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
374 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_NRT
&& vcc
->qos
.txtp
.scr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
376 || (vcc
->qos
.txtp
.traffic_class
== ATM_UBR_PLUS
&& vcc
->qos
.txtp
.min_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
)) )
383 /* check existing vpi,vci */
384 conn
= find_vpivci(vpi
, vci
);
390 /* check whether it need to enable irq */
391 if ( g_atm_priv_data
.conn_table
== 0 )
394 /* allocate connection */
395 for ( conn
= 0; conn
< MAX_PVC_NUMBER
; conn
++ ) {
396 if ( test_and_set_bit(conn
, &g_atm_priv_data
.conn_table
) == 0 ) {
397 g_atm_priv_data
.conn
[conn
].vcc
= vcc
;
401 if ( conn
== MAX_PVC_NUMBER
) {
406 /* reserve bandwidth */
407 switch ( vcc
->qos
.txtp
.traffic_class
) {
410 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.max_pcr
;
414 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.scr
;
418 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.min_pcr
;
423 set_qsb(vcc
, &vcc
->qos
, conn
);
425 /* update atm_vcc structure */
426 vcc
->itf
= (int)vcc
->dev
->dev_data
;
429 set_bit(ATM_VF_READY
, &vcc
->flags
);
432 if ( f_enable_irq
) {
433 ifx_atm_alloc_tx
= atm_alloc_tx
;
435 *MBOX_IGU1_ISRC
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
436 *MBOX_IGU1_IER
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
438 enable_irq(PPE_MAILBOX_IGU1_INT
);
442 WTX_QUEUE_CONFIG(conn
+ FIRST_QSB_QID
)->sbid
= (int)vcc
->dev
->dev_data
;
445 set_htu_entry(vpi
, vci
, conn
, vcc
->qos
.aal
== ATM_AAL5
? 1 : 0, 0);
447 *MBOX_IGU1_ISRC
|= (1 << (conn
+ FIRST_QSB_QID
+ 16));
448 *MBOX_IGU1_IER
|= (1 << (conn
+ FIRST_QSB_QID
+ 16));
456 static void ppe_close(struct atm_vcc
*vcc
)
460 struct connection
*connection
;
464 /* get connection id */
465 conn
= find_vcc(vcc
);
467 pr_err("can't find vcc\n");
470 connection
= &g_atm_priv_data
.conn
[conn
];
471 port
= &g_atm_priv_data
.port
[connection
->port
];
474 clear_htu_entry(conn
);
476 /* release connection */
477 connection
->vcc
= NULL
;
478 connection
->aal5_vcc_crc_err
= 0;
479 connection
->aal5_vcc_oversize_sdu
= 0;
480 clear_bit(conn
, &g_atm_priv_data
.conn_table
);
483 if ( g_atm_priv_data
.conn_table
== 0 ) {
484 disable_irq(PPE_MAILBOX_IGU1_INT
);
485 ifx_atm_alloc_tx
= NULL
;
488 /* release bandwidth */
489 switch ( vcc
->qos
.txtp
.traffic_class
)
493 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.max_pcr
;
497 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.scr
;
501 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.min_pcr
;
505 /* wait for incoming packets to be processed by upper layers */
506 tasklet_unlock_wait(&g_dma_tasklet
);
512 static int ppe_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
)
519 /* the len of the data without offset and header */
522 struct tx_descriptor reg_desc
= {0};
523 struct tx_inband_header
*header
;
525 if ( vcc
== NULL
|| skb
== NULL
)
529 conn
= find_vcc(vcc
);
536 pr_debug("not in showtime\n");
541 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
542 required
= sizeof(*header
) + byteoff
;
543 if (!skb_clone_writable(skb
, required
)) {
547 if (skb_headroom(skb
) < required
)
548 expand_by
= required
- skb_headroom(skb
);
550 ret
= pskb_expand_head(skb
, expand_by
, 0, GFP_ATOMIC
);
552 printk("pskb_expand_head failed.\n");
553 atm_free_tx_skb_vcc(skb
, vcc
);
559 header
= (void *)skb_push(skb
, byteoff
+ TX_INBAND_HEADER_LENGTH
);
562 if ( vcc
->qos
.aal
== ATM_AAL5
) {
563 /* setup inband trailer */
566 header
->pad
= aal5_fill_pattern
;
569 /* setup cell header */
570 header
->clp
= (vcc
->atm_options
& ATM_ATMOPT_CLP
) ? 1 : 0;
571 header
->pti
= ATM_PTI_US0
;
572 header
->vci
= vcc
->vci
;
573 header
->vpi
= vcc
->vpi
;
576 /* setup descriptor */
577 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
578 reg_desc
.datalen
= datalen
;
579 reg_desc
.byteoff
= byteoff
;
582 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
583 reg_desc
.datalen
= skb
->len
;
584 reg_desc
.byteoff
= byteoff
;
590 reg_desc
.sop
= reg_desc
.eop
= 1;
592 spin_lock_irqsave(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
593 desc_base
= get_tx_desc(conn
);
594 if ( desc_base
< 0 ) {
595 spin_unlock_irqrestore(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
596 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
600 /* update descriptor send pointer */
601 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
602 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
603 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
605 spin_unlock_irqrestore(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
608 atomic_inc(&vcc
->stats
->tx
);
609 if ( vcc
->qos
.aal
== ATM_AAL5
)
610 g_atm_priv_data
.wtx_pdu
++;
611 /* write discriptor to memory and write back cache */
612 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
613 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
615 mailbox_signal(conn
, 1);
622 pr_err("FIND_VCC_FAIL\n");
623 g_atm_priv_data
.wtx_err_pdu
++;
624 dev_kfree_skb_any(skb
);
628 if ( vcc
->qos
.aal
== ATM_AAL5
)
629 g_atm_priv_data
.wtx_drop_pdu
++;
631 atomic_inc(&vcc
->stats
->tx_err
);
632 dev_kfree_skb_any(skb
);
636 /* operation and maintainance */
637 static int ppe_send_oam(struct atm_vcc
*vcc
, void *cell
, int flags
)
640 struct uni_cell_header
*uni_cell_header
= (struct uni_cell_header
*)cell
;
643 struct tx_descriptor reg_desc
= {0};
645 if ( ((uni_cell_header
->pti
== ATM_PTI_SEGF5
|| uni_cell_header
->pti
== ATM_PTI_E2EF5
)
646 && find_vpivci(uni_cell_header
->vpi
, uni_cell_header
->vci
) < 0)
647 || ((uni_cell_header
->vci
== 0x03 || uni_cell_header
->vci
== 0x04)
648 && find_vpi(uni_cell_header
->vpi
) < 0) )
650 g_atm_priv_data
.wtx_err_oam
++;
655 pr_err("not in showtime\n");
656 g_atm_priv_data
.wtx_drop_oam
++;
660 conn
= find_vcc(vcc
);
662 pr_err("FIND_VCC_FAIL\n");
663 g_atm_priv_data
.wtx_drop_oam
++;
667 skb
= alloc_skb_tx(CELL_SIZE
);
669 pr_err("ALLOC_SKB_TX_FAIL\n");
670 g_atm_priv_data
.wtx_drop_oam
++;
673 skb_put(skb
, CELL_SIZE
);
674 memcpy(skb
->data
, cell
, CELL_SIZE
);
676 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
677 reg_desc
.datalen
= CELL_SIZE
;
678 reg_desc
.byteoff
= 0;
683 reg_desc
.sop
= reg_desc
.eop
= 1;
685 desc_base
= get_tx_desc(conn
);
686 if ( desc_base
< 0 ) {
687 dev_kfree_skb_any(skb
);
688 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
689 g_atm_priv_data
.wtx_drop_oam
++;
694 atomic_inc(&vcc
->stats
->tx
);
696 /* update descriptor send pointer */
697 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
698 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
699 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
701 /* write discriptor to memory and write back cache */
702 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
703 dma_cache_wback((unsigned long)skb
->data
, CELL_SIZE
);
705 mailbox_signal(conn
, 1);
707 g_atm_priv_data
.wtx_oam
++;
713 static int ppe_change_qos(struct atm_vcc
*vcc
, struct atm_qos
*qos
, int flags
)
717 if ( vcc
== NULL
|| qos
== NULL
)
720 conn
= find_vcc(vcc
);
724 set_qsb(vcc
, qos
, conn
);
729 static inline void adsl_led_flash(void)
731 ifx_mei_atm_led_blink();
736 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
738 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
739 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
740 * ret --- ppe_u64_t, pointer to a variable to hold result
744 static inline void u64_add_u32(ppe_u64_t opt1
, unsigned int opt2
, ppe_u64_t
*ret
)
746 ret
->l
= opt1
.l
+ opt2
;
747 if ( ret
->l
< opt1
.l
|| ret
->l
< opt2
)
751 static inline struct sk_buff
* alloc_skb_rx(void)
755 skb
= dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
757 /* must be burst length alignment */
758 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
759 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
760 /* pub skb in reserved area "skb->data - 4" */
761 *((struct sk_buff
**)skb
->data
- 1) = skb
;
762 /* write back and invalidate cache */
763 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
764 /* invalidate cache */
765 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
766 dma_cache_inv((unsigned long)skb
->data
, LESS_CACHE_INV_LEN
);
768 dma_cache_inv((unsigned long)skb
->data
, RX_DMA_CH_AAL_BUF_SIZE
);
774 static inline struct sk_buff
* alloc_skb_tx(unsigned int size
)
778 /* allocate memory including header and padding */
779 size
+= TX_INBAND_HEADER_LENGTH
+ MAX_TX_PACKET_ALIGN_BYTES
+ MAX_TX_PACKET_PADDING_BYTES
;
780 size
&= ~(DATA_BUFFER_ALIGNMENT
- 1);
781 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
782 /* must be burst length alignment */
784 skb_reserve(skb
, (~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1)) + TX_INBAND_HEADER_LENGTH
);
788 struct sk_buff
* atm_alloc_tx(struct atm_vcc
*vcc
, unsigned int size
)
793 /* oversize packet */
794 if ( size
> aal5s_max_packet_size
) {
795 pr_err("atm_alloc_tx: oversize packet\n");
798 /* send buffer overflow */
799 if ( sk_wmem_alloc_get(sk_atm(vcc
)) && !atm_may_send(vcc
, size
) ) {
800 pr_err("atm_alloc_tx: send buffer overflow\n");
803 conn
= find_vcc(vcc
);
805 pr_err("atm_alloc_tx: unknown VCC\n");
809 skb
= dev_alloc_skb(size
);
811 pr_err("atm_alloc_tx: sk buffer is used up\n");
815 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0))
816 refcount_add(skb
->truesize
, &sk_atm(vcc
)->sk_wmem_alloc
);
818 atomic_add(skb
->truesize
, &sk_atm(vcc
)->sk_wmem_alloc
);
824 static inline void atm_free_tx_skb_vcc(struct sk_buff
*skb
, struct atm_vcc
*vcc
)
826 if ( vcc
->pop
!= NULL
)
829 dev_kfree_skb_any(skb
);
832 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int dataptr
)
834 unsigned int skb_dataptr
;
837 skb_dataptr
= ((dataptr
- 1) << 2) | KSEG1
;
838 skb
= *(struct sk_buff
**)skb_dataptr
;
840 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
841 ASSERT(((unsigned int)skb
->data
| KSEG1
) == ((dataptr
<< 2) | KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
846 static inline int get_tx_desc(unsigned int conn
)
849 struct connection
*p_conn
= &g_atm_priv_data
.conn
[conn
];
851 if ( p_conn
->tx_desc
[p_conn
->tx_desc_pos
].own
== 0 ) {
852 desc_base
= p_conn
->tx_desc_pos
;
853 if ( ++(p_conn
->tx_desc_pos
) == dma_tx_descriptor_length
)
854 p_conn
->tx_desc_pos
= 0;
860 static void free_tx_ring(unsigned int queue
)
864 struct connection
*conn
= &g_atm_priv_data
.conn
[queue
];
870 spin_lock_irqsave(&conn
->lock
, flags
);
872 for (i
= 0; i
< dma_tx_descriptor_length
; i
++) {
873 if (conn
->tx_desc
[i
].own
== 0 && conn
->tx_skb
[i
] != NULL
) {
874 skb
= conn
->tx_skb
[i
];
875 conn
->tx_skb
[i
] = NULL
;
876 atm_free_tx_skb_vcc(skb
, ATM_SKB(skb
)->vcc
);
879 spin_unlock_irqrestore(&conn
->lock
, flags
);
882 static void mailbox_tx_handler(unsigned int queue_bitmap
)
887 /* only get valid queues */
888 queue_bitmap
&= g_atm_priv_data
.conn_table
;
890 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
891 if (queue_bitmap
& bit
)
896 static inline void mailbox_oam_rx_handler(void)
898 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
)->vlddes
;
899 struct rx_descriptor reg_desc
;
900 struct uni_cell_header
*header
;
905 for ( i
= 0; i
< vlddes
; i
++ ) {
906 unsigned int loop_count
= 0;
909 reg_desc
= g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
];
910 if ( ++loop_count
== 1000 )
912 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
913 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.oam_desc_pos
);
915 header
= (struct uni_cell_header
*)&g_atm_priv_data
.oam_buf
[g_atm_priv_data
.oam_desc_pos
* RX_DMA_CH_OAM_BUF_SIZE
];
917 if ( header
->pti
== ATM_PTI_SEGF5
|| header
->pti
== ATM_PTI_E2EF5
)
918 conn
= find_vpivci(header
->vpi
, header
->vci
);
919 else if ( header
->vci
== 0x03 || header
->vci
== 0x04 )
920 conn
= find_vpi(header
->vpi
);
924 if ( conn
>= 0 && g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
925 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
927 if ( vcc
->push_oam
!= NULL
)
928 vcc
->push_oam(vcc
, header
);
930 ifx_push_oam((unsigned char *)header
);
932 g_atm_priv_data
.wrx_oam
++;
936 g_atm_priv_data
.wrx_drop_oam
++;
938 reg_desc
.byteoff
= 0;
939 reg_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
943 g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
] = reg_desc
;
944 if ( ++g_atm_priv_data
.oam_desc_pos
== RX_DMA_CH_OAM_DESC_LEN
)
945 g_atm_priv_data
.oam_desc_pos
= 0;
947 dma_cache_inv((unsigned long)header
, CELL_SIZE
);
948 mailbox_signal(RX_DMA_CH_OAM
, 0);
952 static inline void mailbox_aal_rx_handler(void)
954 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
)->vlddes
;
955 struct rx_descriptor reg_desc
;
958 struct sk_buff
*skb
, *new_skb
;
959 struct rx_inband_trailer
*trailer
;
962 for ( i
= 0; i
< vlddes
; i
++ ) {
963 unsigned int loop_count
= 0;
966 reg_desc
= g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
];
967 if ( ++loop_count
== 1000 )
969 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
970 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.aal_desc_pos
);
974 if ( g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
975 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
977 skb
= get_skb_rx_pointer(reg_desc
.dataptr
);
979 if ( reg_desc
.err
) {
980 if ( vcc
->qos
.aal
== ATM_AAL5
) {
981 trailer
= (struct rx_inband_trailer
*)((unsigned int)skb
->data
+ ((reg_desc
.byteoff
+ reg_desc
.datalen
+ MAX_RX_PACKET_PADDING_BYTES
) & ~MAX_RX_PACKET_PADDING_BYTES
));
982 if ( trailer
->stw_crc
)
983 g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
++;
984 if ( trailer
->stw_ovz
)
985 g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
++;
986 g_atm_priv_data
.wrx_drop_pdu
++;
989 atomic_inc(&vcc
->stats
->rx_drop
);
990 atomic_inc(&vcc
->stats
->rx_err
);
993 } else if ( atm_charge(vcc
, skb
->truesize
) ) {
994 new_skb
= alloc_skb_rx();
995 if ( new_skb
!= NULL
) {
996 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
997 if ( reg_desc
.byteoff
+ reg_desc
.datalen
> LESS_CACHE_INV_LEN
)
998 dma_cache_inv((unsigned long)skb
->data
+ LESS_CACHE_INV_LEN
, reg_desc
.byteoff
+ reg_desc
.datalen
- LESS_CACHE_INV_LEN
);
1001 skb_reserve(skb
, reg_desc
.byteoff
);
1002 skb_put(skb
, reg_desc
.datalen
);
1003 ATM_SKB(skb
)->vcc
= vcc
;
1005 vcc
->push(vcc
, skb
);
1007 if ( vcc
->qos
.aal
== ATM_AAL5
)
1008 g_atm_priv_data
.wrx_pdu
++;
1010 atomic_inc(&vcc
->stats
->rx
);
1013 reg_desc
.dataptr
= (unsigned int)new_skb
->data
>> 2;
1015 atm_return(vcc
, skb
->truesize
);
1016 if ( vcc
->qos
.aal
== ATM_AAL5
)
1017 g_atm_priv_data
.wrx_drop_pdu
++;
1019 atomic_inc(&vcc
->stats
->rx_drop
);
1022 if ( vcc
->qos
.aal
== ATM_AAL5
)
1023 g_atm_priv_data
.wrx_drop_pdu
++;
1025 atomic_inc(&vcc
->stats
->rx_drop
);
1028 g_atm_priv_data
.wrx_drop_pdu
++;
1031 reg_desc
.byteoff
= 0;
1032 reg_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
1036 g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
] = reg_desc
;
1037 if ( ++g_atm_priv_data
.aal_desc_pos
== dma_rx_descriptor_length
)
1038 g_atm_priv_data
.aal_desc_pos
= 0;
1040 mailbox_signal(RX_DMA_CH_AAL
, 0);
1044 static void do_ppe_tasklet(unsigned long data
)
1046 unsigned int irqs
= *MBOX_IGU1_ISR
;
1047 *MBOX_IGU1_ISRC
= *MBOX_IGU1_ISR
;
1049 if (irqs
& (1 << RX_DMA_CH_AAL
))
1050 mailbox_aal_rx_handler();
1051 if (irqs
& (1 << RX_DMA_CH_OAM
))
1052 mailbox_oam_rx_handler();
1054 /* any valid tx irqs */
1055 if ((irqs
>> (FIRST_QSB_QID
+ 16)) & g_atm_priv_data
.conn_table
)
1056 mailbox_tx_handler(irqs
>> (FIRST_QSB_QID
+ 16));
1058 if ((*MBOX_IGU1_ISR
& ((1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
))) != 0)
1059 tasklet_schedule(&g_dma_tasklet
);
1060 else if (*MBOX_IGU1_ISR
>> (FIRST_QSB_QID
+ 16)) /* TX queue */
1061 tasklet_schedule(&g_dma_tasklet
);
1063 enable_irq(PPE_MAILBOX_IGU1_INT
);
1066 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
1068 if ( !*MBOX_IGU1_ISR
)
1071 disable_irq_nosync(PPE_MAILBOX_IGU1_INT
);
1072 tasklet_schedule(&g_dma_tasklet
);
1077 static inline void mailbox_signal(unsigned int queue
, int is_tx
)
1082 while ( MBOX_IGU3_ISR_ISR(queue
+ FIRST_QSB_QID
+ 16) && count
> 0 )
1084 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
+ FIRST_QSB_QID
+ 16);
1086 while ( MBOX_IGU3_ISR_ISR(queue
) && count
> 0 )
1088 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
);
1091 ASSERT(count
> 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue
, is_tx
, IFX_REG_R32(MBOX_IGU3_ISR
));
1094 static void set_qsb(struct atm_vcc
*vcc
, struct atm_qos
*qos
, unsigned int queue
)
1096 struct clk
*fpi_clk
= clk_get_fpi();
1097 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1098 unsigned int qsb_qid
= queue
+ FIRST_QSB_QID
;
1099 union qsb_queue_parameter_table qsb_queue_parameter_table
= {{0}};
1100 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table
= {{0}};
1105 * Peak Cell Rate (PCR) Limiter
1107 if ( qos
->txtp
.max_pcr
== 0 )
1108 qsb_queue_parameter_table
.bit
.tp
= 0; /* disable PCR limiter */
1110 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1111 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.max_pcr
+ 1;
1112 /* check if overflow takes place */
1113 qsb_queue_parameter_table
.bit
.tp
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1116 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1117 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1118 // Send packets to these two PVCs at same time, it trigger strange behavior.
1119 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1120 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1121 // To work around, create UBR always with max_pcr.
1122 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1123 if ( qos
->txtp
.traffic_class
== ATM_UBR
&& qsb_queue_parameter_table
.bit
.tp
== 0 ) {
1124 int port
= g_atm_priv_data
.conn
[queue
].port
;
1125 unsigned int max_pcr
= g_atm_priv_data
.port
[port
].tx_max_cell_rate
+ 1000;
1127 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / max_pcr
+ 1;
1128 if ( tmp
> QSB_TP_TS_MAX
)
1129 tmp
= QSB_TP_TS_MAX
;
1132 qsb_queue_parameter_table
.bit
.tp
= tmp
;
1137 * Weighted Fair Queueing Factor (WFQF)
1139 switch ( qos
->txtp
.traffic_class
) {
1142 /* real time queue gets weighted fair queueing bypass */
1143 qsb_queue_parameter_table
.bit
.wfqf
= 0;
1147 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1148 /* WFQF is maximum cell rate / garenteed cell rate */
1149 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1150 if ( qos
->txtp
.min_pcr
== 0 )
1151 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1153 tmp
= QSB_GCR_MIN
* QSB_WFQ_NONUBR_MAX
/ qos
->txtp
.min_pcr
;
1155 qsb_queue_parameter_table
.bit
.wfqf
= 1;
1156 else if ( tmp
> QSB_WFQ_NONUBR_MAX
)
1157 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1159 qsb_queue_parameter_table
.bit
.wfqf
= tmp
;
1164 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_UBR_BYPASS
;
1168 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1170 if ( qos
->txtp
.traffic_class
== ATM_VBR_RT
|| qos
->txtp
.traffic_class
== ATM_VBR_NRT
) {
1172 if ( qos
->txtp
.scr
== 0 ) {
1174 /* disable shaper */
1175 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1176 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1179 /* Cell Loss Priority (CLP) */
1180 if ( (vcc
->atm_options
& ATM_ATMOPT_CLP
) )
1182 qsb_queue_parameter_table
.bit
.vbr
= 1;
1185 qsb_queue_parameter_table
.bit
.vbr
= 0;
1186 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1187 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.scr
+ 1;
1188 qsb_queue_vbr_parameter_table
.bit
.ts
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1189 tmp
= (qos
->txtp
.mbs
- 1) * (qsb_queue_vbr_parameter_table
.bit
.ts
- qsb_queue_parameter_table
.bit
.tp
) / 64;
1191 qsb_queue_vbr_parameter_table
.bit
.taus
= 1;
1192 else if ( tmp
> QSB_TAUS_MAX
)
1193 qsb_queue_vbr_parameter_table
.bit
.taus
= QSB_TAUS_MAX
;
1195 qsb_queue_vbr_parameter_table
.bit
.taus
= tmp
;
1199 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1200 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1203 /* Queue Parameter Table (QPT) */
1204 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QPT_SET_MASK
);
1205 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_parameter_table
.dword
);
1206 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1207 /* Queue VBR Paramter Table (QVPT) */
1208 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QVPT_SET_MASK
);
1209 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table
.dword
);
1210 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1214 static void qsb_global_set(void)
1216 struct clk
*fpi_clk
= clk_get_fpi();
1217 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1219 unsigned int tmp1
, tmp2
, tmp3
;
1221 *QSB_ICDV
= QSB_ICDV_TAU_SET(qsb_tau
);
1222 *QSB_SBL
= QSB_SBL_SBL_SET(qsb_srvm
);
1223 *QSB_CFG
= QSB_CFG_TSTEPC_SET(qsb_tstep
>> 1);
1226 * set SCT and SPT per port
1228 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ ) {
1229 if ( g_atm_priv_data
.port
[i
].tx_max_cell_rate
!= 0 ) {
1230 tmp1
= ((qsb_clk
* qsb_tstep
) >> 1) / g_atm_priv_data
.port
[i
].tx_max_cell_rate
;
1231 tmp2
= tmp1
>> 6; /* integer value of Tsb */
1232 tmp3
= (tmp1
& ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1233 /* carry over to integer part (?) */
1234 if ( tmp3
== (1 << 6) ) {
1241 /* 2. write value to data transfer register */
1242 /* 3. start the tranfer */
1243 /* SCT (FracRate) */
1244 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SCT_MASK
);
1245 *QSB_RTD
= QSB_RTD_TTV_SET(tmp3
);
1246 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1247 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT
) |
1248 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1249 QSB_RAMAC_TESEL_SET(i
& 0x01);
1250 /* SPT (SBV + PN + IntRage) */
1251 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SPT_MASK
);
1252 *QSB_RTD
= QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID
| QSB_SPT_PN_SET(i
& 0x01) | QSB_SPT_INTRATE_SET(tmp2
));
1253 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1254 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT
) |
1255 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1256 QSB_RAMAC_TESEL_SET(i
& 0x01);
1261 static inline void set_htu_entry(unsigned int vpi
, unsigned int vci
, unsigned int queue
, int aal5
, int is_retx
)
1263 struct htu_entry htu_entry
= {
1265 clp
: is_retx
? 0x01 : 0x00,
1266 pid
: g_atm_priv_data
.conn
[queue
].port
& 0x01,
1272 struct htu_mask htu_mask
= {
1278 pti_mask
: 0x03, // 0xx, user data
1281 struct htu_result htu_result
= {
1285 type
: aal5
? 0x00 : 0x01,
1290 *HTU_RESULT(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1291 *HTU_MASK(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1292 *HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1295 static inline void clear_htu_entry(unsigned int queue
)
1297 HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
)->vld
= 0;
1300 static void validate_oam_htu_entry(void)
1302 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 1;
1303 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 1;
1304 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 1;
1307 static void invalidate_oam_htu_entry(void)
1309 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 0;
1310 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 0;
1311 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 0;
1314 static inline int find_vpi(unsigned int vpi
)
1319 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1320 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1321 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1322 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
)
1329 static inline int find_vpivci(unsigned int vpi
, unsigned int vci
)
1334 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1335 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1336 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1337 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
1338 && vci
== g_atm_priv_data
.conn
[i
].vcc
->vci
)
1345 static inline int find_vcc(struct atm_vcc
*vcc
)
1350 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1351 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1352 && g_atm_priv_data
.conn
[i
].vcc
== vcc
)
1359 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *buf
)
1362 unsigned int major
, minor
;
1364 ops
->fw_ver(&major
, &minor
);
1366 len
+= sprintf(buf
+ len
, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR
, IFX_ATM_VER_MID
, IFX_ATM_VER_MINOR
);
1367 len
+= sprintf(buf
+ len
, " ATM (A1) firmware version %d.%d\n", major
, minor
);
1372 static inline void check_parameters(void)
1374 /* Please refer to Amazon spec 15.4 for setting these values. */
1377 if ( qsb_tstep
< 1 )
1379 else if ( qsb_tstep
> 4 )
1381 else if ( qsb_tstep
== 3 )
1384 /* There is a delay between PPE write descriptor and descriptor is */
1385 /* really stored in memory. Host also has this delay when writing */
1386 /* descriptor. So PPE will use this value to determine if the write */
1387 /* operation makes effect. */
1388 if ( write_descriptor_delay
< 0 )
1389 write_descriptor_delay
= 0;
1391 if ( aal5_fill_pattern
< 0 )
1392 aal5_fill_pattern
= 0;
1394 aal5_fill_pattern
&= 0xFF;
1396 /* Because of the limitation of length field in descriptors, the packet */
1397 /* size could not be larger than 64K minus overhead size. */
1398 if ( aal5r_max_packet_size
< 0 )
1399 aal5r_max_packet_size
= 0;
1400 else if ( aal5r_max_packet_size
>= 65535 - MAX_RX_FRAME_EXTRA_BYTES
)
1401 aal5r_max_packet_size
= 65535 - MAX_RX_FRAME_EXTRA_BYTES
;
1402 if ( aal5r_min_packet_size
< 0 )
1403 aal5r_min_packet_size
= 0;
1404 else if ( aal5r_min_packet_size
> aal5r_max_packet_size
)
1405 aal5r_min_packet_size
= aal5r_max_packet_size
;
1406 if ( aal5s_max_packet_size
< 0 )
1407 aal5s_max_packet_size
= 0;
1408 else if ( aal5s_max_packet_size
>= 65535 - MAX_TX_FRAME_EXTRA_BYTES
)
1409 aal5s_max_packet_size
= 65535 - MAX_TX_FRAME_EXTRA_BYTES
;
1410 if ( aal5s_min_packet_size
< 0 )
1411 aal5s_min_packet_size
= 0;
1412 else if ( aal5s_min_packet_size
> aal5s_max_packet_size
)
1413 aal5s_min_packet_size
= aal5s_max_packet_size
;
1415 if ( dma_rx_descriptor_length
< 2 )
1416 dma_rx_descriptor_length
= 2;
1417 if ( dma_tx_descriptor_length
< 2 )
1418 dma_tx_descriptor_length
= 2;
1419 if ( dma_rx_clp1_descriptor_threshold
< 0 )
1420 dma_rx_clp1_descriptor_threshold
= 0;
1421 else if ( dma_rx_clp1_descriptor_threshold
> dma_rx_descriptor_length
)
1422 dma_rx_clp1_descriptor_threshold
= dma_rx_descriptor_length
;
1424 if ( dma_tx_descriptor_length
< 2 )
1425 dma_tx_descriptor_length
= 2;
1428 static inline int init_priv_data(void)
1432 struct rx_descriptor rx_desc
= {0};
1433 struct sk_buff
*skb
;
1434 volatile struct tx_descriptor
*p_tx_desc
;
1435 struct sk_buff
**ppskb
;
1437 // clear atm private data structure
1438 memset(&g_atm_priv_data
, 0, sizeof(g_atm_priv_data
));
1440 // allocate memory for RX (AAL) descriptors
1441 p
= kzalloc(dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1444 dma_cache_wback_inv((unsigned long)p
, dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1445 g_atm_priv_data
.aal_desc_base
= p
;
1446 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1447 g_atm_priv_data
.aal_desc
= (volatile struct rx_descriptor
*)p
;
1449 // allocate memory for RX (OAM) descriptors
1450 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1453 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1454 g_atm_priv_data
.oam_desc_base
= p
;
1455 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1456 g_atm_priv_data
.oam_desc
= (volatile struct rx_descriptor
*)p
;
1458 // allocate memory for RX (OAM) buffer
1459 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
, GFP_KERNEL
);
1462 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
1463 g_atm_priv_data
.oam_buf_base
= p
;
1464 p
= (void *)(((unsigned int)p
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1));
1465 g_atm_priv_data
.oam_buf
= p
;
1467 // allocate memory for TX descriptors
1468 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1471 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
);
1472 g_atm_priv_data
.tx_desc_base
= p
;
1474 // allocate memory for TX skb pointers
1475 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4, GFP_KERNEL
);
1478 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4);
1479 g_atm_priv_data
.tx_skb_base
= p
;
1481 // setup RX (AAL) descriptors
1486 rx_desc
.byteoff
= 0;
1489 rx_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
1490 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1491 skb
= alloc_skb_rx();
1494 rx_desc
.dataptr
= ((unsigned int)skb
->data
>> 2) & 0x0FFFFFFF;
1495 g_atm_priv_data
.aal_desc
[i
] = rx_desc
;
1498 // setup RX (OAM) descriptors
1499 p
= (void *)((unsigned int)g_atm_priv_data
.oam_buf
| KSEG1
);
1504 rx_desc
.byteoff
= 0;
1507 rx_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
1508 for ( i
= 0; i
< RX_DMA_CH_OAM_DESC_LEN
; i
++ ) {
1509 rx_desc
.dataptr
= ((unsigned int)p
>> 2) & 0x0FFFFFFF;
1510 g_atm_priv_data
.oam_desc
[i
] = rx_desc
;
1511 p
= (void *)((unsigned int)p
+ RX_DMA_CH_OAM_BUF_SIZE
);
1514 // setup TX descriptors and skb pointers
1515 p_tx_desc
= (volatile struct tx_descriptor
*)((((unsigned int)g_atm_priv_data
.tx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1516 ppskb
= (struct sk_buff
**)(((unsigned int)g_atm_priv_data
.tx_skb_base
+ 3) & ~3);
1517 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1518 spin_lock_init(&g_atm_priv_data
.conn
[i
].lock
);
1519 g_atm_priv_data
.conn
[i
].tx_desc
= &p_tx_desc
[i
* dma_tx_descriptor_length
];
1520 g_atm_priv_data
.conn
[i
].tx_skb
= &ppskb
[i
* dma_tx_descriptor_length
];
1523 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1524 g_atm_priv_data
.port
[i
].tx_max_cell_rate
= DEFAULT_TX_LINK_RATE
;
1529 static inline void clear_priv_data(void)
1532 struct sk_buff
*skb
;
1534 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1535 if ( g_atm_priv_data
.conn
[i
].tx_skb
!= NULL
) {
1536 for ( j
= 0; j
< dma_tx_descriptor_length
; j
++ )
1537 if ( g_atm_priv_data
.conn
[i
].tx_skb
[j
] != NULL
)
1538 dev_kfree_skb_any(g_atm_priv_data
.conn
[i
].tx_skb
[j
]);
1542 if ( g_atm_priv_data
.tx_skb_base
!= NULL
)
1543 kfree(g_atm_priv_data
.tx_skb_base
);
1545 if ( g_atm_priv_data
.tx_desc_base
!= NULL
)
1546 kfree(g_atm_priv_data
.tx_desc_base
);
1548 if ( g_atm_priv_data
.oam_buf_base
!= NULL
)
1549 kfree(g_atm_priv_data
.oam_buf_base
);
1551 if ( g_atm_priv_data
.oam_desc_base
!= NULL
)
1552 kfree(g_atm_priv_data
.oam_desc_base
);
1554 if ( g_atm_priv_data
.aal_desc_base
!= NULL
) {
1555 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1556 if ( g_atm_priv_data
.aal_desc
[i
].sop
|| g_atm_priv_data
.aal_desc
[i
].eop
) { // descriptor initialized
1557 skb
= get_skb_rx_pointer(g_atm_priv_data
.aal_desc
[i
].dataptr
);
1558 dev_kfree_skb_any(skb
);
1561 kfree(g_atm_priv_data
.aal_desc_base
);
1565 static inline void init_rx_tables(void)
1568 struct wrx_queue_config wrx_queue_config
= {0};
1569 struct wrx_dma_channel_config wrx_dma_channel_config
= {0};
1570 struct htu_entry htu_entry
= {0};
1571 struct htu_result htu_result
= {0};
1572 struct htu_mask htu_mask
= {
1585 *CFG_WRX_HTUTS
= MAX_PVC_NUMBER
+ OAM_HTU_ENTRY_NUMBER
;
1586 #ifndef CONFIG_AMAZON_SE
1587 *CFG_WRX_QNUM
= MAX_QUEUE_NUMBER
;
1589 *CFG_WRX_DCHNUM
= RX_DMA_CH_TOTAL
;
1590 *WRX_DMACH_ON
= (1 << RX_DMA_CH_TOTAL
) - 1;
1591 *WRX_HUNT_BITTH
= DEFAULT_RX_HUNT_BITTH
;
1594 * WRX Queue Configuration Table
1596 wrx_queue_config
.uumask
= 0xFF;
1597 wrx_queue_config
.cpimask
= 0xFF;
1598 wrx_queue_config
.uuexp
= 0;
1599 wrx_queue_config
.cpiexp
= 0;
1600 wrx_queue_config
.mfs
= aal5r_max_packet_size
;
1601 wrx_queue_config
.oversize
= aal5r_max_packet_size
;
1602 wrx_queue_config
.undersize
= aal5r_min_packet_size
;
1603 wrx_queue_config
.errdp
= aal5r_drop_error_packet
;
1604 wrx_queue_config
.dmach
= RX_DMA_CH_AAL
;
1605 for ( i
= 0; i
< MAX_QUEUE_NUMBER
; i
++ )
1606 *WRX_QUEUE_CONFIG(i
) = wrx_queue_config
;
1607 WRX_QUEUE_CONFIG(OAM_RX_QUEUE
)->dmach
= RX_DMA_CH_OAM
;
1610 * WRX DMA Channel Configuration Table
1612 wrx_dma_channel_config
.chrl
= 0;
1613 wrx_dma_channel_config
.clp1th
= dma_rx_clp1_descriptor_threshold
;
1614 wrx_dma_channel_config
.mode
= 0;
1615 wrx_dma_channel_config
.rlcfg
= 0;
1617 wrx_dma_channel_config
.deslen
= RX_DMA_CH_OAM_DESC_LEN
;
1618 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.oam_desc
>> 2) & 0x0FFFFFFF;
1619 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
) = wrx_dma_channel_config
;
1621 wrx_dma_channel_config
.deslen
= dma_rx_descriptor_length
;
1622 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.aal_desc
>> 2) & 0x0FFFFFFF;
1623 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
) = wrx_dma_channel_config
;
1628 for (i
= 0; i
< MAX_PVC_NUMBER
; i
++) {
1629 htu_result
.qid
= (unsigned int)i
;
1631 *HTU_ENTRY(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1632 *HTU_MASK(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1633 *HTU_RESULT(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1637 htu_entry
.vci
= 0x03;
1638 htu_mask
.pid_mask
= 0x03;
1639 htu_mask
.vpi_mask
= 0xFF;
1640 htu_mask
.vci_mask
= 0x0000;
1641 htu_mask
.pti_mask
= 0x07;
1642 htu_result
.cellid
= OAM_RX_QUEUE
;
1643 htu_result
.type
= 1;
1645 htu_result
.qid
= OAM_RX_QUEUE
;
1646 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY
) = htu_result
;
1647 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY
) = htu_mask
;
1648 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
) = htu_entry
;
1649 htu_entry
.vci
= 0x04;
1650 htu_result
.cellid
= OAM_RX_QUEUE
;
1651 htu_result
.type
= 1;
1653 htu_result
.qid
= OAM_RX_QUEUE
;
1654 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY
) = htu_result
;
1655 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY
) = htu_mask
;
1656 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
) = htu_entry
;
1657 htu_entry
.vci
= 0x00;
1658 htu_entry
.pti
= 0x04;
1659 htu_mask
.vci_mask
= 0xFFFF;
1660 htu_mask
.pti_mask
= 0x01;
1661 htu_result
.cellid
= OAM_RX_QUEUE
;
1662 htu_result
.type
= 1;
1664 htu_result
.qid
= OAM_RX_QUEUE
;
1665 *HTU_RESULT(OAM_F5_HTU_ENTRY
) = htu_result
;
1666 *HTU_MASK(OAM_F5_HTU_ENTRY
) = htu_mask
;
1667 *HTU_ENTRY(OAM_F5_HTU_ENTRY
) = htu_entry
;
1670 static inline void init_tx_tables(void)
1673 struct wtx_queue_config wtx_queue_config
= {0};
1674 struct wtx_dma_channel_config wtx_dma_channel_config
= {0};
1675 struct wtx_port_config wtx_port_config
= {
1684 *CFG_WTX_DCHNUM
= MAX_TX_DMA_CHANNEL_NUMBER
;
1685 *WTX_DMACH_ON
= ((1 << MAX_TX_DMA_CHANNEL_NUMBER
) - 1) ^ ((1 << FIRST_QSB_QID
) - 1);
1686 *CFG_WRDES_DELAY
= write_descriptor_delay
;
1689 * WTX Port Configuration Table
1691 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1692 *WTX_PORT_CONFIG(i
) = wtx_port_config
;
1695 * WTX Queue Configuration Table
1697 wtx_queue_config
.qsben
= 1;
1698 wtx_queue_config
.sbid
= 0;
1699 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1700 wtx_queue_config
.qsb_vcid
= i
;
1701 *WTX_QUEUE_CONFIG(i
) = wtx_queue_config
;
1705 * WTX DMA Channel Configuration Table
1707 wtx_dma_channel_config
.mode
= 0;
1708 wtx_dma_channel_config
.deslen
= 0;
1709 wtx_dma_channel_config
.desba
= 0;
1710 for ( i
= 0; i
< FIRST_QSB_QID
; i
++ )
1711 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1712 /* normal connection */
1713 wtx_dma_channel_config
.deslen
= dma_tx_descriptor_length
;
1714 for ( ; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1715 wtx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.conn
[i
- FIRST_QSB_QID
].tx_desc
>> 2) & 0x0FFFFFFF;
1716 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1720 static int atm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
1724 ASSERT(port_cell
!= NULL
, "port_cell is NULL");
1725 ASSERT(xdata_addr
!= NULL
, "xdata_addr is NULL");
1727 for ( j
= 0; j
< ATM_PORT_NUMBER
&& j
< port_cell
->port_num
; j
++ )
1728 if ( port_cell
->tx_link_rate
[j
] > 0 )
1730 for ( i
= 0; i
< ATM_PORT_NUMBER
&& i
< port_cell
->port_num
; i
++ )
1731 g_atm_priv_data
.port
[i
].tx_max_cell_rate
=
1732 port_cell
->tx_link_rate
[i
] > 0 ? port_cell
->tx_link_rate
[i
] : port_cell
->tx_link_rate
[j
];
1736 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ )
1737 if ( g_atm_priv_data
.conn
[i
].vcc
!= NULL
)
1738 set_qsb(g_atm_priv_data
.conn
[i
].vcc
, &g_atm_priv_data
.conn
[i
].vcc
->qos
, i
);
1740 // TODO: ReTX set xdata_addr
1741 g_xdata_addr
= xdata_addr
;
1745 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1746 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_FOUND
);
1748 #if defined(CONFIG_VR9)
1749 IFX_REG_W32(0x0F, UTP_CFG
);
1752 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1753 g_atm_priv_data
.port
[0].tx_max_cell_rate
,
1754 g_atm_priv_data
.port
[1].tx_max_cell_rate
,
1755 (unsigned int)g_xdata_addr
);
1760 static int atm_showtime_exit(void)
1767 #if defined(CONFIG_VR9)
1768 IFX_REG_W32(0x00, UTP_CFG
);
1771 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1772 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_LOST
);
1775 g_xdata_addr
= NULL
;
1776 printk("leave showtime\n");
1780 extern struct ltq_atm_ops ar9_ops
;
1781 extern struct ltq_atm_ops vr9_ops
;
1782 extern struct ltq_atm_ops danube_ops
;
1783 extern struct ltq_atm_ops ase_ops
;
1785 static const struct of_device_id ltq_atm_match
[] = {
1786 #ifdef CONFIG_DANUBE
1787 { .compatible
= "lantiq,ppe-danube", .data
= &danube_ops
},
1788 #elif defined CONFIG_AMAZON_SE
1789 { .compatible
= "lantiq,ppe-ase", .data
= &ase_ops
},
1790 #elif defined CONFIG_AR9
1791 { .compatible
= "lantiq,ppe-arx100", .data
= &ar9_ops
},
1792 #elif defined CONFIG_VR9
1793 { .compatible
= "lantiq,ppe-xrx200", .data
= &vr9_ops
},
1797 MODULE_DEVICE_TABLE(of
, ltq_atm_match
);
1799 static int ltq_atm_probe(struct platform_device
*pdev
)
1801 const struct of_device_id
*match
;
1802 struct ltq_atm_ops
*ops
= NULL
;
1805 struct port_cell_info port_cell
= {0};
1808 match
= of_match_device(ltq_atm_match
, &pdev
->dev
);
1810 dev_err(&pdev
->dev
, "failed to find matching device\n");
1813 ops
= (struct ltq_atm_ops
*) match
->data
;
1817 ret
= init_priv_data();
1819 pr_err("INIT_PRIV_DATA_FAIL\n");
1820 goto INIT_PRIV_DATA_FAIL
;
1827 /* create devices */
1828 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ ) {
1829 g_atm_priv_data
.port
[port_num
].dev
= atm_dev_register("ifxmips_atm", NULL
, &g_ifx_atm_ops
, -1, NULL
);
1830 if ( !g_atm_priv_data
.port
[port_num
].dev
) {
1831 pr_err("failed to register atm device %d!\n", port_num
);
1833 goto ATM_DEV_REGISTER_FAIL
;
1835 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vpi_bits
= 8;
1836 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vci_bits
= 16;
1837 g_atm_priv_data
.port
[port_num
].dev
->link_rate
= g_atm_priv_data
.port
[port_num
].tx_max_cell_rate
;
1838 g_atm_priv_data
.port
[port_num
].dev
->dev_data
= (void*)port_num
;
1840 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1841 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_LOST
);
1846 /* register interrupt handler */
1847 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1848 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, 0, "atm_mailbox_isr", &g_atm_priv_data
);
1850 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, IRQF_DISABLED
, "atm_mailbox_isr", &g_atm_priv_data
);
1853 if ( ret
== -EBUSY
) {
1854 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1856 pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT
);
1858 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1860 disable_irq(PPE_MAILBOX_IGU1_INT
);
1863 ret
= ops
->start(0);
1865 pr_err("ifx_pp32_start fail!\n");
1866 goto PP32_START_FAIL
;
1869 port_cell
.port_num
= ATM_PORT_NUMBER
;
1870 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &g_xdata_addr
);
1872 atm_showtime_enter(&port_cell
, &g_xdata_addr
);
1877 validate_oam_htu_entry();
1879 ifx_mei_atm_showtime_enter
= atm_showtime_enter
;
1880 ifx_mei_atm_showtime_exit
= atm_showtime_exit
;
1882 ifx_atm_version(ops
, ver_str
);
1883 printk(KERN_INFO
"%s", ver_str
);
1884 platform_set_drvdata(pdev
, ops
);
1885 printk("ifxmips_atm: ATM init succeed\n");
1890 free_irq(PPE_MAILBOX_IGU1_INT
, &g_atm_priv_data
);
1891 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1892 ATM_DEV_REGISTER_FAIL
:
1893 while ( port_num
-- > 0 )
1894 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1895 INIT_PRIV_DATA_FAIL
:
1897 printk("ifxmips_atm: ATM init failed\n");
1901 static int ltq_atm_remove(struct platform_device
*pdev
)
1904 struct ltq_atm_ops
*ops
= platform_get_drvdata(pdev
);
1906 ifx_mei_atm_showtime_enter
= NULL
;
1907 ifx_mei_atm_showtime_exit
= NULL
;
1909 invalidate_oam_htu_entry();
1913 free_irq(PPE_MAILBOX_IGU1_INT
, &g_atm_priv_data
);
1915 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1916 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1925 static struct platform_driver ltq_atm_driver
= {
1926 .probe
= ltq_atm_probe
,
1927 .remove
= ltq_atm_remove
,
1930 .owner
= THIS_MODULE
,
1931 .of_match_table
= ltq_atm_match
,
1935 module_platform_driver(ltq_atm_driver
);
1937 MODULE_LICENSE("Dual BSD/GPL");