target/linux/ar7-2.6/files/arch/mips/ar7/vlynq-pci.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/pci.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <asm/ar7/vlynq.h>
  26
  27 #define VLYNQ_PCI_SLOTS 2
  28
  29 struct vlynq_reg_config {
  30         u32 offset;
  31         u32 value;
  32 };
  33
  34 struct vlynq_pci_config {
  35         u32 chip_id;
  36         char name[32];
  37         struct vlynq_mapping rx_mapping[4];
  38         int irq;
  39         int irq_type;
  40         u32 chip;
  41         u32 class;
  42         int num_regs;
  43         struct vlynq_reg_config regs[10];
  44 };
  45
  46 struct vlynq_pci_private {
  47         u32 latency;
  48         u32 cache_line;
  49         u32 command;
  50         u32 sz_mask;
  51         struct vlynq_pci_config *config;
  52 };
  53
  54 static struct vlynq_pci_config known_devices[] = {
  55         {
  56                 .chip_id = 0x00000009, .name = "TI ACX111",
  57                 .rx_mapping = {
  58                         { .size = 0x22000, .offset = 0xf0000000 },
  59                         { .size = 0x40000, .offset = 0xc0000000 },
  60                         { .size = 0x0, .offset = 0x0 },
  61                         { .size = 0x0, .offset = 0x0 },
  62                 },
  63                 .irq = 0, .chip = 0x9066104c,
  64                 .class = PCI_CLASS_NETWORK_OTHER,
  65                 .num_regs = 5,
  66                 .regs = {
  67                         { .offset = 0x790, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
  68                         { .offset = 0x794, .value = (0xd0000000 - (ARCH_PFN_OFFSET << PAGE_SHIFT)) },
  69                         { .offset = 0x740, .value = 0 },
  70                         { .offset = 0x744, .value = 0x00010000 },
  71                         { .offset = 0x764, .value = 0x00010000 },
  72                 },
  73         },
  74 };
  75
  76 static struct vlynq_device *slots[VLYNQ_PCI_SLOTS] = { NULL, };
  77
  78 static struct resource vlynq_io_resource = {
  79         .start  = 0x00000000,
  80         .end    = 0x00000000,
  81         .name   = "pci IO space",
  82         .flags  = IORESOURCE_IO
  83 };
  84
  85 static struct resource vlynq_mem_resource = {
  86         .start  = 0x00000000,
  87         .end    = 0x00000000,
  88         .name   = "pci memory space",
  89         .flags  = IORESOURCE_MEM
  90 };
  91
  92 static inline u32 vlynq_get_mapped(struct vlynq_device *dev, int res)
  93 {
  94         int i;
  95         struct vlynq_pci_private *priv = dev->priv;
  96         u32 ret = dev->mem_start;
  97         if (!priv->config->rx_mapping[res].size) return 0;
  98         for (i = 0; i < res; i++)
  99                 ret += priv->config->rx_mapping[i].size;
 100
 101         return ret;
 102 }
 103
 104 static inline u32 vlynq_read(u32 val, int size) {
 105         switch (size) {
 106         case 1:
 107                 return *(u8 *)&val;
 108         case 2:
 109                 return *(u16 *)&val;
 110         }
 111         return val;
 112 }
 113
 114 static int vlynq_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
 115 {
 116         struct vlynq_device *dev;
 117         struct vlynq_pci_private *priv;
 118         int resno, slot = PCI_SLOT(devfn);
 119
 120         if ((size == 2) && (where & 1))
 121                 return PCIBIOS_BAD_REGISTER_NUMBER;
 122         else if ((size == 4) && (where & 3))
 123                 return PCIBIOS_BAD_REGISTER_NUMBER;
 124
 125         if (slot >= VLYNQ_PCI_SLOTS)
 126                 return PCIBIOS_DEVICE_NOT_FOUND;
 127
 128         dev = slots[slot];
 129
 130         if (!dev || (PCI_FUNC(devfn) > 0))
 131                 return PCIBIOS_DEVICE_NOT_FOUND;
 132
 133         priv = dev->priv;
 134
 135         switch (where) {
 136         case PCI_VENDOR_ID:
 137                 *val = vlynq_read(priv->config->chip, size);
 138                 break;
 139         case PCI_DEVICE_ID:
 140                 *val = priv->config->chip & 0xffff;
 141         case PCI_COMMAND:
 142                 *val = priv->command;
 143         case PCI_STATUS:
 144 /*              *val = PCI_STATUS_CAP_LIST;*/
 145                 *val = 0;
 146                 break;
 147         case PCI_CLASS_REVISION:
 148                 *val = priv->config->class;
 149                 break;
 150         case PCI_LATENCY_TIMER:
 151                 *val = priv->latency;
 152                 break;
 153         case PCI_HEADER_TYPE:
 154                 *val = PCI_HEADER_TYPE_NORMAL;
 155                 break;
 156         case PCI_CACHE_LINE_SIZE:
 157                 *val = priv->cache_line;
 158                 break;
 159         case PCI_BASE_ADDRESS_0:
 160         case PCI_BASE_ADDRESS_1:
 161         case PCI_BASE_ADDRESS_2:
 162         case PCI_BASE_ADDRESS_3:
 163                 resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 164                 if (priv->sz_mask & (1 << resno)) {
 165                         priv->sz_mask &= ~(1 << resno);
 166                         *val = priv->config->rx_mapping[resno].size;
 167                 } else {
 168                         *val = vlynq_get_mapped(dev, resno);
 169                 }
 170                 break;
 171         case PCI_BASE_ADDRESS_4:
 172         case PCI_BASE_ADDRESS_5:
 173         case PCI_SUBSYSTEM_VENDOR_ID:
 174         case PCI_SUBSYSTEM_ID:
 175         case PCI_ROM_ADDRESS:
 176         case PCI_INTERRUPT_LINE:
 177         case PCI_CARDBUS_CIS:
 178         case PCI_CAPABILITY_LIST:
 179         case PCI_INTERRUPT_PIN:
 180                 *val = 0;
 181                 break;
 182         default:
 183                 printk("%s: Read of unknown register 0x%x (size %d)\n",
 184                        dev->dev.bus_id, where, size);
 185                 return PCIBIOS_BAD_REGISTER_NUMBER;
 186         }
 187         return PCIBIOS_SUCCESSFUL;
 188 }
 189
 190 static int vlynq_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 191 {
 192         struct vlynq_device *dev;
 193         struct vlynq_pci_private *priv;
 194         int resno, slot = PCI_SLOT(devfn);
 195
 196         if ((size == 2) && (where & 1))
 197                 return PCIBIOS_BAD_REGISTER_NUMBER;
 198         else if ((size == 4) && (where & 3))
 199                 return PCIBIOS_BAD_REGISTER_NUMBER;
 200
 201         if (slot >= VLYNQ_PCI_SLOTS)
 202                 return PCIBIOS_DEVICE_NOT_FOUND;
 203
 204         dev = slots[slot];
 205
 206         if (!dev || (PCI_FUNC(devfn) > 0))
 207                 return PCIBIOS_DEVICE_NOT_FOUND;
 208
 209         priv = dev->priv;
 210
 211         switch (where) {
 212         case PCI_VENDOR_ID:
 213         case PCI_DEVICE_ID:
 214         case PCI_STATUS:
 215         case PCI_CLASS_REVISION:
 216         case PCI_HEADER_TYPE:
 217         case PCI_CACHE_LINE_SIZE:
 218         case PCI_SUBSYSTEM_VENDOR_ID:
 219         case PCI_SUBSYSTEM_ID:
 220         case PCI_INTERRUPT_LINE:
 221         case PCI_INTERRUPT_PIN:
 222         case PCI_CARDBUS_CIS:
 223         case PCI_CAPABILITY_LIST:
 224                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 225         case PCI_COMMAND:
 226                 priv->command = val;
 227         case PCI_LATENCY_TIMER:
 228                 priv->latency = val;
 229                 break;
 230         case PCI_BASE_ADDRESS_0:
 231         case PCI_BASE_ADDRESS_1:
 232         case PCI_BASE_ADDRESS_2:
 233         case PCI_BASE_ADDRESS_3:
 234                 if (val == 0xffffffff) {
 235                         resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 236                         priv->sz_mask |= (1 << resno);
 237                         break;
 238                 }
 239         case PCI_BASE_ADDRESS_4:
 240         case PCI_BASE_ADDRESS_5:
 241         case PCI_ROM_ADDRESS:
 242                 break;
 243         default:
 244                 printk("%s: Write to unknown register 0x%x (size %d) value=0x%x\n",
 245                        dev->dev.bus_id, where, size, val);
 246                 return PCIBIOS_BAD_REGISTER_NUMBER;
 247         }
 248         return PCIBIOS_SUCCESSFUL;
 249 }
 250
 251 static struct pci_ops vlynq_pci_ops = {
 252         vlynq_config_read,
 253         vlynq_config_write
 254 };
 255
 256 static struct pci_controller vlynq_controller = {
 257         .pci_ops        = &vlynq_pci_ops,
 258         .io_resource    = &vlynq_io_resource,
 259         .mem_resource   = &vlynq_mem_resource,
 260 };
 261
 262 static int vlynq_pci_probe(struct vlynq_device *dev)
 263 {
 264         int result, i;
 265         u32 chip_id, addr;
 266         struct vlynq_pci_private *priv;
 267         struct vlynq_mapping mapping[4] = { { 0, }, };
 268         struct vlynq_pci_config *config = NULL;
 269
 270         result = vlynq_set_local_irq(dev, 31);
 271         if (result)
 272                 return result;
 273
 274         result = vlynq_set_remote_irq(dev, 30);
 275         if (result)
 276                 return result;
 277
 278         result = vlynq_device_enable(dev);
 279         if (result)
 280                 return result;
 281
 282         chip_id = vlynq_remote_id(dev);
 283         for (i = 0; i < ARRAY_SIZE(known_devices); i++)
 284                 if (chip_id == known_devices[i].chip_id)
 285                         config = &known_devices[i];
 286
 287         if (!config) {
 288                 printk("vlynq-pci: skipping unknown device "
 289                        "%04x:%04x at %s\n", chip_id >> 16,
 290                        chip_id & 0xffff, dev->dev.bus_id);
 291                 result = -ENODEV;
 292                 goto fail;
 293         }
 294
 295         printk("vlynq-pci: attaching device %s at %s\n",
 296                config->name, dev->dev.bus_id);
 297
 298         priv = kmalloc(sizeof(struct vlynq_pci_private), GFP_KERNEL);
 299         if (!priv) {
 300                 printk(KERN_ERR "%s: failed to allocate private data\n",
 301                        dev->dev.bus_id);
 302                 result = -ENOMEM;
 303                 goto fail;
 304         }
 305
 306         memset(priv, 0, sizeof(struct vlynq_pci_private));
 307         priv->latency = 64;
 308         priv->cache_line = 32;
 309         priv->config = config;
 310
 311         mapping[0].offset = ARCH_PFN_OFFSET << PAGE_SHIFT;
 312         mapping[0].size = 0x02000000;
 313         vlynq_set_local_mapping(dev, dev->mem_start, mapping);
 314         vlynq_set_remote_mapping(dev, 0, config->rx_mapping);
 315
 316         addr = (u32)ioremap_nocache(dev->mem_start, 0x10000);
 317         if (!addr) {
 318                 printk(KERN_ERR "%s: failed to remap io memory\n",
 319                        dev->dev.bus_id);
 320                 result = -ENXIO;
 321                 goto fail;
 322         }
 323
 324         for (i = 0; i < config->num_regs; i++)
 325                 *(volatile u32 *)(addr + config->regs[i].offset) =
 326                         config->regs[i].value;
 327
 328         dev->priv = priv;
 329         for (i = 0; i < VLYNQ_PCI_SLOTS; i++) {
 330                 if (!slots[i]) {
 331                         slots[i] = dev;
 332                         break;
 333                 }
 334         }
 335
 336         return 0;
 337
 338 fail:
 339         vlynq_device_disable(dev);
 340
 341         return result;
 342 }
 343
 344 static int vlynq_pci_remove(struct vlynq_device *dev)
 345 {
 346         int i;
 347         struct vlynq_pci_private *priv = dev->priv;
 348
 349         for (i = 0; i < VLYNQ_PCI_SLOTS; i++)
 350                 if (slots[i] == dev)
 351                         slots[i] = NULL;
 352
 353         vlynq_device_disable(dev);
 354         kfree(priv);
 355
 356         return 0;
 357 }
 358
 359 static struct vlynq_driver vlynq_pci = {
 360         .name = "PCI over VLYNQ emulation",
 361         .probe = vlynq_pci_probe,
 362         .remove = vlynq_pci_remove,
 363 };
 364
 365 int vlynq_pci_init(void)
 366 {
 367         int res;
 368         res = vlynq_register_driver(&vlynq_pci);
 369         if (res)
 370                 return res;
 371
 372         register_pci_controller(&vlynq_controller);
 373
 374         return 0;
 375 }
 376
 377 int pcibios_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 378 {
 379         struct vlynq_device *dev;
 380         struct vlynq_pci_private *priv;
 381
 382         dev = slots[slot];
 383
 384         if (!dev)
 385                 return 0;
 386
 387         priv = dev->priv;
 388
 389         return vlynq_virq_to_irq(dev, priv->config->irq);
 390 }
 391
 392 /* Do platform specific device initialization at pci_enable_device() time */
 393 int pcibios_plat_dev_init(struct pci_dev *dev)
 394 {
 395         return 0;
 396 }