target/linux/ar7-2.6/files/include/asm-mips/ar7/ar7.h

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #ifndef __AR7_H__
  22 #define __AR7_H__
  23
  24 #include <linux/delay.h>
  25 #include <asm/addrspace.h>
  26 #include <asm/io.h>
  27
  28 #define AR7_REGS_BASE 0x08610000
  29
  30 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
  31 #define AR7_REGS_EMIF   (AR7_REGS_BASE + 0x0800)
  32 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
  33 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
  34 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
  35 #define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
  36 #define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
  37 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
  38 #define AR7_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
  39 #define AR7_REGS_I2C    (AR7_REGS_BASE + 0x1000)
  40 #define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
  41 #define AR7_REGS_DMA    (AR7_REGS_BASE + 0x1400)
  42 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
  43 #define AR7_REGS_BIST   (AR7_REGS_BASE + 0x1700)
  44 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  45 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1A00)
  46 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
  47 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1E00)
  48 #define AR7_REGS_FSER   (AR7_REGS_BASE + 0x2000)
  49 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
  50 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
  51
  52 #define  AR7_RESET_PEREPHERIAL 0x0
  53 #define  AR7_RESET_SOFTWARE    0x4
  54 #define  AR7_RESET_STATUS      0x8
  55
  56 #define AR7_RESET_BIT_CPMAC_LO 17
  57 #define AR7_RESET_BIT_CPMAC_HI 21
  58 #define AR7_RESET_BIT_MDIO     22
  59 #define AR7_RESET_BIT_EPHY     26
  60
  61 /* GPIO control registers */
  62 #define  AR7_GPIO_INPUT  0x0
  63 #define  AR7_GPIO_OUTPUT 0x4
  64 #define  AR7_GPIO_DIR    0x8
  65 #define  AR7_GPIO_ENABLE 0xC
  66
  67 #define AR7_GPIO_BIT_STATUS_LED   8
  68
  69 #define AR7_CHIP_7100 0x18
  70 #define AR7_CHIP_7200 0x2b
  71 #define AR7_CHIP_7300 0x05
  72
  73 /* Interrupts */
  74 #define AR7_IRQ_UART0  15
  75 #define AR7_IRQ_UART1  16
  76
  77 struct plat_cpmac_data {
  78         int reset_bit;
  79         int power_bit;
  80         u32 phy_mask;
  81         char dev_addr[6];
  82 };
  83
  84 struct plat_dsl_data {
  85         int reset_bit_dsl;
  86         int reset_bit_sar;
  87 };
  88
  89 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
  90
  91 static inline u16 ar7_chip_id(void)
  92 {
  93         return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
  94 }
  95
  96 static inline u8 ar7_chip_rev(void)
  97 {
  98         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
  99 }
 100
 101 static inline int ar7_cpu_freq(void)
 102 {
 103         return ar7_cpu_clock;
 104 }
 105
 106 static inline int ar7_bus_freq(void)
 107 {
 108         return ar7_bus_clock;
 109 }
 110
 111 static inline int ar7_vbus_freq(void)
 112 {
 113         return ar7_bus_clock / 2;
 114 }
 115 #define ar7_cpmac_freq ar7_vbus_freq
 116
 117 static inline int ar7_dsp_freq(void)
 118 {
 119         return ar7_dsp_clock;
 120 }
 121
 122 static inline int ar7_has_high_cpmac(void)
 123 {
 124         u16 chip_id = ar7_chip_id();
 125         switch (chip_id) {
 126         case AR7_CHIP_7100:
 127         case AR7_CHIP_7200:
 128                 return 0;
 129         default:
 130                 return 1;
 131         }
 132 }
 133 #define ar7_has_high_vlynq ar7_has_high_cpmac
 134
 135 static inline void ar7_device_enable(u32 bit)
 136 {
 137         void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 138         writel(readl(reset_reg) | (1 << bit), reset_reg);
 139         mdelay(20);
 140 }
 141
 142 static inline void ar7_device_disable(u32 bit)
 143 {
 144         void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 145         writel(readl(reset_reg) & ~(1 << bit), reset_reg);
 146         mdelay(20);
 147 }
 148
 149 static inline void ar7_device_reset(u32 bit)
 150 {
 151         ar7_device_disable(bit);
 152         ar7_device_enable(bit);
 153 }
 154
 155 static inline void ar7_device_on(u32 bit)
 156 {
 157         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 158         writel(readl(power_reg) | (1 << bit), power_reg);
 159         mdelay(20);
 160 }
 161
 162 static inline void ar7_device_off(u32 bit)
 163 {
 164         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 165         writel(readl(power_reg) & ~(1 << bit), power_reg);
 166         mdelay(20);
 167 }
 168
 169 #endif