target/linux/ar71xx/files-3.2/arch/mips/ath79/mach-dir-615-e4.c

   1 /*
   2  *  D-Link DIR-615 rev. E4 board support
   3  *
   4  *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/partitions.h>
  14
  15 #include <asm/mach-ath79/ath79.h>
  16
  17 #include "dev-ap9x-pci.h"
  18 #include "dev-eth.h"
  19 #include "dev-gpio-buttons.h"
  20 #include "dev-leds-gpio.h"
  21 #include "dev-m25p80.h"
  22 #include "machtypes.h"
  23 #include "nvram.h"
  24
  25 #define DIR_615_E4_GPIO_LED_WPS                 0
  26 #define DIR_615_E4_GPIO_LED_POWER_AMBER         1
  27 #define DIR_615_E4_GPIO_LED_POWER_GREEN         6
  28 #define DIR_615_E4_GPIO_LED_WAN_AMBER           7
  29 #define DIR_615_E4_GPIO_LED_WAN_GREEN           17
  30 #define DIR_615_E4_GPIO_LED_LAN1_GREEN          13
  31 #define DIR_615_E4_GPIO_LED_LAN2_GREEN          14
  32 #define DIR_615_E4_GPIO_LED_LAN3_GREEN          15
  33 #define DIR_615_E4_GPIO_LED_LAN4_GREEN          16
  34
  35 #define DIR_615_E4_GPIO_BTN_RESET               8
  36 #define DIR_615_E4_GPIO_BTN_WPS                 12
  37
  38 #define DIR_615_E4_KEYS_POLL_INTERVAL   20
  39 #define DIR_615_E4_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_E4_KEYS_POLL_INTERVAL)
  40
  41 #define DIR_615_E4_NVRAM_ADDR   0x1f030000
  42 #define DIR_615_E4_NVRAM_SIZE   0x10000
  43
  44 static struct mtd_partition dir_615_e4_partitions[] = {
  45         {
  46                 .name           = "u-boot",
  47                 .offset         = 0,
  48                 .size           = 0x030000,
  49                 .mask_flags     = MTD_WRITEABLE,
  50         }, {
  51                 .name           = "nvram",
  52                 .offset         = 0x030000,
  53                 .size           = 0x010000,
  54         }, {
  55                 .name           = "kernel",
  56                 .offset         = 0x040000,
  57                 .size           = 0x0e0000,
  58         }, {
  59                 .name           = "rootfs",
  60                 .offset         = 0x120000,
  61                 .size           = 0x2c0000,
  62         }, {
  63                 .name           = "mac",
  64                 .offset         = 0x3e0000,
  65                 .size           = 0x010000,
  66                 .mask_flags     = MTD_WRITEABLE,
  67         }, {
  68                 .name           = "art",
  69                 .offset         = 0x3f0000,
  70                 .size           = 0x010000,
  71                 .mask_flags     = MTD_WRITEABLE,
  72         }, {
  73                 .name           = "firmware",
  74                 .offset         = 0x040000,
  75                 .size           = 0x3a0000,
  76         }
  77 };
  78
  79 static struct flash_platform_data dir_615_e4_flash_data = {
  80         .parts          = dir_615_e4_partitions,
  81         .nr_parts       = ARRAY_SIZE(dir_615_e4_partitions),
  82 };
  83
  84
  85 static struct gpio_led dir_615_e4_leds_gpio[] __initdata = {
  86         {
  87                 .name           = "d-link:green:power",
  88                 .gpio           = DIR_615_E4_GPIO_LED_POWER_GREEN,
  89         }, {
  90                 .name           = "d-link:amber:power",
  91                 .gpio           = DIR_615_E4_GPIO_LED_POWER_AMBER,
  92         }, {
  93                 .name           = "d-link:green:wan",
  94                 .gpio           = DIR_615_E4_GPIO_LED_WAN_GREEN,
  95                 .active_low     = 1,
  96         }, {
  97                 .name           = "d-link:amber:wan",
  98                 .gpio           = DIR_615_E4_GPIO_LED_WAN_AMBER,
  99         }, {
 100                 .name           = "d-link:green:lan1",
 101                 .gpio           = DIR_615_E4_GPIO_LED_LAN1_GREEN,
 102                 .active_low     = 1,
 103         }, {
 104                 .name           = "d-link:green:lan2",
 105                 .gpio           = DIR_615_E4_GPIO_LED_LAN2_GREEN,
 106                 .active_low     = 1,
 107         }, {
 108                 .name           = "d-link:green:lan3",
 109                 .gpio           = DIR_615_E4_GPIO_LED_LAN3_GREEN,
 110                 .active_low     = 1,
 111         }, {
 112                 .name           = "d-link:green:lan4",
 113                 .gpio           = DIR_615_E4_GPIO_LED_LAN4_GREEN,
 114                 .active_low     = 1,
 115         }, {
 116                 .name           = "d-link:blue:wps",
 117                 .gpio           = DIR_615_E4_GPIO_LED_WPS,
 118                 .active_low     = 1,
 119         }
 120 };
 121
 122 static struct gpio_keys_button dir_615_e4_gpio_keys[] __initdata = {
 123         {
 124                 .desc           = "reset",
 125                 .type           = EV_KEY,
 126                 .code           = KEY_RESTART,
 127                 .debounce_interval = DIR_615_E4_KEYS_DEBOUNCE_INTERVAL,
 128                 .gpio           = DIR_615_E4_GPIO_BTN_RESET,
 129                 .active_low     = 1,
 130         }, {
 131                 .desc           = "wps",
 132                 .type           = EV_KEY,
 133                 .code           = KEY_WPS_BUTTON,
 134                 .debounce_interval = DIR_615_E4_KEYS_DEBOUNCE_INTERVAL,
 135                 .gpio           = DIR_615_E4_GPIO_BTN_WPS,
 136                 .active_low     = 1,
 137         }
 138 };
 139
 140 static void __init dir_615_e4_setup(void)
 141 {
 142         const char *nvram = (char *) KSEG1ADDR(DIR_615_E4_NVRAM_ADDR);
 143         u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
 144         u8 mac_buff[6];
 145         u8 *mac = NULL;
 146
 147         if (ath79_nvram_parse_mac_addr(nvram, DIR_615_E4_NVRAM_SIZE,
 148                                        "lan_mac=", mac_buff) == 0) {
 149                 ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0);
 150                 ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1);
 151                 mac = mac_buff;
 152         }
 153
 154         ath79_register_m25p80(&dir_615_e4_flash_data);
 155
 156         ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615_e4_leds_gpio),
 157                                  dir_615_e4_leds_gpio);
 158
 159         ath79_register_gpio_keys_polled(-1, DIR_615_E4_KEYS_POLL_INTERVAL,
 160                                         ARRAY_SIZE(dir_615_e4_gpio_keys),
 161                                         dir_615_e4_gpio_keys);
 162
 163         ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
 164         ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
 165
 166         ath79_register_mdio(0, 0x0);
 167
 168         /* LAN ports */
 169         ath79_register_eth(1);
 170
 171         /* WAN port */
 172         ath79_register_eth(0);
 173
 174         ap9x_pci_setup_wmac_led_pin(0, 1);
 175         ap91_pci_init(ee, mac);
 176 }
 177
 178 MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4",
 179              dir_615_e4_setup);