target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c

   1 /*
   2  *  OpenMesh OM5P-ACv2 support
   3  *
   4  *  Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
   5  *  Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com>
   6  *  Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/gpio.h>
  14 #include <linux/mdio-gpio.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/partitions.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/i2c.h>
  19 #include <linux/i2c-algo-bit.h>
  20 #include <linux/i2c-gpio.h>
  21 #include <linux/platform_data/phy-at803x.h>
  22
  23 #include <asm/mach-ath79/ar71xx_regs.h>
  24 #include <asm/mach-ath79/ath79.h>
  25
  26 #include "common.h"
  27 #include "dev-ap9x-pci.h"
  28 #include "dev-eth.h"
  29 #include "dev-gpio-buttons.h"
  30 #include "dev-leds-gpio.h"
  31 #include "dev-m25p80.h"
  32 #include "dev-wmac.h"
  33 #include "machtypes.h"
  34 #include "pci.h"
  35
  36 #define OM5PACV2_GPIO_LED_POWER 14
  37 #define OM5PACV2_GPIO_LED_GREEN 13
  38 #define OM5PACV2_GPIO_LED_RED   23
  39 #define OM5PACV2_GPIO_LED_YELLOW        15
  40 #define OM5PACV2_GPIO_BTN_RESET 1
  41 #define OM5PACV2_GPIO_I2C_SCL   18
  42 #define OM5PACV2_GPIO_I2C_SDA   19
  43 #define OM5PACV2_GPIO_PA_DCDC   2
  44 #define OM5PACV2_GPIO_PA_HIGH   16
  45
  46 #define OM5PACV2_KEYS_POLL_INTERVAL     20      /* msecs */
  47 #define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL)
  48
  49 #define OM5PACV2_WMAC_CALDATA_OFFSET    0x1000
  50
  51 static struct gpio_led om5pacv2_leds_gpio[] __initdata = {
  52         {
  53                 .name           = "om5pac:blue:power",
  54                 .gpio           = OM5PACV2_GPIO_LED_POWER,
  55                 .active_low     = 1,
  56         }, {
  57                 .name           = "om5pac:red:wifi",
  58                 .gpio           = OM5PACV2_GPIO_LED_RED,
  59                 .active_low     = 1,
  60         }, {
  61                 .name           = "om5pac:yellow:wifi",
  62                 .gpio           = OM5PACV2_GPIO_LED_YELLOW,
  63                 .active_low     = 1,
  64         }, {
  65                 .name           = "om5pac:green:wifi",
  66                 .gpio           = OM5PACV2_GPIO_LED_GREEN,
  67                 .active_low     = 1,
  68         }
  69 };
  70
  71 static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = {
  72         {
  73                 .desc           = "reset",
  74                 .type           = EV_KEY,
  75                 .code           = KEY_RESTART,
  76                 .debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL,
  77                 .gpio           = OM5PACV2_GPIO_BTN_RESET,
  78                 .active_low     = 1,
  79         }
  80 };
  81
  82 static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = {
  83         .sda_pin                = OM5PACV2_GPIO_I2C_SDA,
  84         .scl_pin                = OM5PACV2_GPIO_I2C_SCL,
  85         .udelay                 = 10,
  86         .sda_is_open_drain      = 1,
  87         .scl_is_open_drain      = 1,
  88 };
  89
  90 static struct platform_device om5pacv2_i2c_device = {
  91         .name           = "i2c-gpio",
  92         .id             = 0,
  93         .dev            = {
  94                 .platform_data  = &om5pacv2_i2c_device_platdata,
  95         },
  96 };
  97
  98 static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = {
  99         {
 100                 I2C_BOARD_INFO("tmp423", 0x4e),
 101         },
 102 };
 103
 104 static struct flash_platform_data om5pacv2_flash_data = {
 105         .type = "mx25l12805d",
 106 };
 107
 108 static struct at803x_platform_data om5pacv2_an_at803x_data = {
 109         .disable_smarteee = 1,
 110         .enable_rgmii_rx_delay = 1,
 111         .enable_rgmii_tx_delay = 1,
 112 };
 113
 114 static struct at803x_platform_data om5pacv2_an_at8031_data = {
 115         .disable_smarteee = 1,
 116         .enable_rgmii_rx_delay = 1,
 117         .enable_rgmii_tx_delay = 1,
 118 };
 119
 120 static struct mdio_board_info om5pacv2_an_mdio0_info[] = {
 121         {
 122                 .bus_id = "ag71xx-mdio.0",
 123                 .phy_addr = 4,
 124                 .platform_data = &om5pacv2_an_at803x_data,
 125         },
 126         {
 127                 .bus_id = "ag71xx-mdio.1",
 128                 .phy_addr = 1,
 129                 .platform_data = &om5pacv2_an_at8031_data,
 130         },
 131 };
 132
 133 static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask,
 134                                                    unsigned int rxd,
 135                                                    unsigned int rxdv,
 136                                                    unsigned int txd,
 137                                                    unsigned int txe)
 138 {
 139         void __iomem *base;
 140         u32 t;
 141
 142         base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 143
 144         t = mask;
 145         t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
 146         t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
 147         t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
 148         t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
 149
 150         __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 151
 152         iounmap(base);
 153 }
 154
 155 static void __init om5p_acv2_setup(void)
 156 {
 157         u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
 158         u8 mac[6];
 159
 160         /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
 161         ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
 162         ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
 163         ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
 164         gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
 165                          "PA DC/DC");
 166         gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
 167
 168         /* temperature sensor */
 169         platform_device_register(&om5pacv2_i2c_device);
 170         i2c_register_board_info(0, om5pacv2_i2c_devs,
 171                                 ARRAY_SIZE(om5pacv2_i2c_devs));
 172
 173         ath79_register_m25p80(&om5pacv2_flash_data);
 174         ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
 175                                  om5pacv2_leds_gpio);
 176         ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
 177                                         ARRAY_SIZE(om5pacv2_gpio_keys),
 178                                         om5pacv2_gpio_keys);
 179
 180         ath79_init_mac(mac, art, 0x02);
 181         ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
 182
 183         om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
 184         ath79_register_mdio(0, 0x0);
 185         ath79_register_mdio(1, 0x0);
 186
 187         mdiobus_register_board_info(om5pacv2_an_mdio0_info,
 188                                     ARRAY_SIZE(om5pacv2_an_mdio0_info));
 189
 190         ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
 191         ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
 192
 193         /* GMAC0 is connected to the PHY4 */
 194         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 195         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 196         ath79_eth0_data.phy_mask = BIT(4);
 197         ath79_eth0_pll_data.pll_1000 = 0x82000101;
 198         ath79_eth0_pll_data.pll_100 = 0x80000101;
 199         ath79_eth0_pll_data.pll_10 = 0x80001313;
 200         ath79_register_eth(0);
 201
 202         /* GMAC1 is connected to MDIO1 in SGMII mode */
 203         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 204         ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
 205         ath79_eth1_data.phy_mask = BIT(1);
 206         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 207         ath79_eth1_pll_data.pll_100 = 0x80000101;
 208         ath79_eth1_pll_data.pll_10 = 0x80001313;
 209         ath79_eth1_data.speed = SPEED_1000;
 210         ath79_eth1_data.duplex = DUPLEX_FULL;
 211         ath79_register_eth(1);
 212
 213         ath79_register_pci();
 214 }
 215
 216 MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup);