target/linux/aruba-2.6/files/include/asm-mips/idt-boards/rc32434/rc32434_uart.h

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *   UART register definitions
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *
  29  **************************************************************************
  30  * May 2004 rkt, neb.
  31  *
  32  * Initial Release
  33  *
  34  *
  35  *
  36  **************************************************************************
  37  */
  38
  39 #ifndef __IDT_UART_H__
  40 #define __IDT_UART_H__
  41
  42 enum
  43 {
  44         UART0_PhysicalAddress   = 0x1c000000,
  45         UART_PhysicalAddress    = UART0_PhysicalAddress,        // Default
  46
  47         UART0_VirtualAddress    = 0xbc000000,
  48         UART_VirtualAddress     = UART0_VirtualAddress,         // Default
  49 } ;
  50
  51 /*
  52  * Register definitions are in bytes so we can handle endian problems.
  53  */
  54
  55 typedef struct UART_s
  56 {
  57         union
  58         {
  59                 u32 const       uartrb ;        // 0x00 - DLAB=0, read.
  60                 u32             uartth ;        // 0x00 - DLAB=0, write.
  61                 u32             uartdll ;       // 0x00 - DLAB=1, read/write.
  62         } ;
  63
  64         union
  65         {
  66                 u32             uartie ;        // 0x04 - DLAB=0, read/write.
  67                 u32             uartdlh ;       // 0x04 - DLAB=1, read/write.
  68         } ;
  69         union
  70         {
  71                 u32 const       uartii ;        // 0x08 - DLAB=0, read.
  72                 u32             uartfc ;        // 0x08 - DLAB=0, write.
  73         } ;
  74
  75         u32             uartlc ;                // 0x0c
  76         u32             uartmc ;                // 0x10
  77         u32             uartls ;                // 0x14
  78         u32             uartms ;                // 0x18
  79         u32             uarts ;                 // 0x1c
  80 } volatile *UART_t ;
  81
  82 // Reset registers.
  83 typedef u32     volatile *UARTRR_t ;
  84
  85 enum
  86 {
  87         UARTIE_rda_b    = 0,
  88         UARTIE_rda_m    = 0x00000001,
  89         UARTIE_the_b    = 1,
  90         UARTIE_the_m    = 0x00000002,
  91         UARTIE_rls_b    = 2,
  92         UARTIE_rls_m    = 0x00000004,
  93         UARTIE_ems_b    = 3,
  94         UARTIE_ems_m    = 0x00000008,
  95
  96         UARTII_pi_b     = 0,
  97         UARTII_pi_m     = 0x00000001,
  98         UARTII_iid_b    = 1,
  99         UARTII_iid_m    = 0x0000000e,
 100                 UARTII_iid_ms_v         = 0,    // Modem stat-CTS,DSR,RI or DCD.
 101                 UARTII_iid_thre_v       = 1,    // Trans. Holding Reg. empty.
 102                 UARTII_iid_rda_v        = 2,    // Receive data available
 103                 UARTII_iid_rls_v        = 3,    // Overrun, parity, etc, error.
 104                 UARTII_iid_res4_v       = 4,    // reserved.
 105                 UARTII_iid_res5_v       = 5,    // reserved.
 106                 UARTII_iid_cto_v        = 6,    // Character timeout.
 107                 UARTII_iid_res7_v       = 7,    // reserved.
 108
 109         UARTFC_en_b     = 0,
 110         UARTFC_en_m     = 0x00000001,
 111         UARTFC_rr_b     = 1,
 112         UARTFC_rr_m     = 0x00000002,
 113         UARTFC_tr_b     = 2,
 114         UARTFC_tr_m     = 0x00000004,
 115         UARTFC_dms_b    = 3,
 116         UARTFC_dms_m    = 0x00000008,
 117         UARTFC_rt_b     = 6,
 118         UARTFC_rt_m     = 0x000000c0,
 119                 UARTFC_rt_1Byte_v       = 0,
 120                 UARTFC_rt_4Byte_v       = 1,
 121                 UARTFC_rt_8Byte_v       = 2,
 122                 UARTFC_rt_14Byte_v      = 3,
 123
 124         UARTLC_wls_b    = 0,
 125         UARTLC_wls_m    = 0x00000003,
 126                 UARTLC_wls_5Bits_v      = 0,
 127                 UARTLC_wls_6Bits_v      = 1,
 128                 UARTLC_wls_7Bits_v      = 2,
 129                 UARTLC_wls_8Bits_v      = 3,
 130         UARTLC_stb_b    = 2,
 131         UARTLC_stb_m    = 0x00000004,
 132         UARTLC_pen_b    = 3,
 133         UARTLC_pen_m    = 0x00000008,
 134         UARTLC_eps_b    = 4,
 135         UARTLC_eps_m    = 0x00000010,
 136         UARTLC_sp_b     = 5,
 137         UARTLC_sp_m     = 0x00000020,
 138         UARTLC_sb_b     = 6,
 139         UARTLC_sb_m     = 0x00000040,
 140         UARTLC_dlab_b   = 7,
 141         UARTLC_dlab_m   = 0x00000080,
 142
 143         UARTMC_dtr_b    = 0,
 144         UARTMC_dtr_m    = 0x00000001,
 145         UARTMC_rts_b    = 1,
 146         UARTMC_rts_m    = 0x00000002,
 147         UARTMC_o1_b     = 2,
 148         UARTMC_o1_m     = 0x00000004,
 149         UARTMC_o2_b     = 3,
 150         UARTMC_o2_m     = 0x00000008,
 151         UARTMC_lp_b     = 4,
 152         UARTMC_lp_m     = 0x00000010,
 153
 154         UARTLS_dr_b     = 0,
 155         UARTLS_dr_m     = 0x00000001,
 156         UARTLS_oe_b     = 1,
 157         UARTLS_oe_m     = 0x00000002,
 158         UARTLS_pe_b     = 2,
 159         UARTLS_pe_m     = 0x00000004,
 160         UARTLS_fe_b     = 3,
 161         UARTLS_fe_m     = 0x00000008,
 162         UARTLS_bi_b     = 4,
 163         UARTLS_bi_m     = 0x00000010,
 164         UARTLS_thr_b    = 5,
 165         UARTLS_thr_m    = 0x00000020,
 166         UARTLS_te_b     = 6,
 167         UARTLS_te_m     = 0x00000040,
 168         UARTLS_rfe_b    = 7,
 169         UARTLS_rfe_m    = 0x00000080,
 170
 171         UARTMS_dcts_b   = 0,
 172         UARTMS_dcts_m   = 0x00000001,
 173         UARTMS_ddsr_b   = 1,
 174         UARTMS_ddsr_m   = 0x00000002,
 175         UARTMS_teri_b   = 2,
 176         UARTMS_teri_m   = 0x00000004,
 177         UARTMS_ddcd_b   = 3,
 178         UARTMS_ddcd_m   = 0x00000008,
 179         UARTMS_cts_b    = 4,
 180         UARTMS_cts_m    = 0x00000010,
 181         UARTMS_dsr_b    = 5,
 182         UARTMS_dsr_m    = 0x00000020,
 183         UARTMS_ri_b     = 6,
 184         UARTMS_ri_m     = 0x00000040,
 185         UARTMS_dcd_b    = 7,
 186         UARTMS_dcd_m    = 0x00000080,
 187 } ;
 188
 189 #endif  // __IDT_UART_H__